[MSP430] Add missing instruction forms
* Add missing mm, [r|m]n, [r|m]p instruction forms.
* Fix bit16mc instruction.
Patch by Kristina Bessonova!
Differential Revision: https://reviews.llvm.org/D56546
llvm-svn: 350902
diff --git a/llvm/test/CodeGen/MSP430/Inst16mm.ll b/llvm/test/CodeGen/MSP430/Inst16mm.ll
index 21fab42..af00a18 100644
--- a/llvm/test/CodeGen/MSP430/Inst16mm.ll
+++ b/llvm/test/CodeGen/MSP430/Inst16mm.ll
@@ -67,3 +67,22 @@
; CHECK-DAG: mov 2(r1), 6(r1)
; CHECK-DAG: mov 0(r1), 4(r1)
}
+
+define void @cmp(i16* %g, i16* %i) {
+entry:
+; CHECK-LABEL: cmp:
+; CHECK: cmp 8(r12), 4(r13)
+ %add.ptr = getelementptr inbounds i16, i16* %g, i16 4
+ %0 = load i16, i16* %add.ptr, align 2
+ %add.ptr1 = getelementptr inbounds i16, i16* %i, i16 2
+ %1 = load i16, i16* %add.ptr1, align 2
+ %cmp = icmp sgt i16 %0, %1
+ br i1 %cmp, label %if.then, label %if.end
+
+if.then: ; preds = %entry
+ store i16 0, i16* %g, align 2
+ br label %if.end
+
+if.end: ; preds = %if.then, %entry
+ ret void
+}
diff --git a/llvm/test/CodeGen/MSP430/Inst8mm.ll b/llvm/test/CodeGen/MSP430/Inst8mm.ll
index b9848dc..5709728 100644
--- a/llvm/test/CodeGen/MSP430/Inst8mm.ll
+++ b/llvm/test/CodeGen/MSP430/Inst8mm.ll
@@ -53,3 +53,21 @@
ret void
}
+define void @cmp(i8* %g, i8* %i) {
+entry:
+; CHECK-LABEL: cmp:
+; CHECK: cmp.b 4(r12), 2(r13)
+ %add.ptr = getelementptr inbounds i8, i8* %g, i16 4
+ %0 = load i8, i8* %add.ptr, align 1
+ %add.ptr1 = getelementptr inbounds i8, i8* %i, i16 2
+ %1 = load i8, i8* %add.ptr1, align 1
+ %cmp = icmp sgt i8 %0, %1
+ br i1 %cmp, label %if.then, label %if.end
+
+if.then: ; preds = %entry
+ store i8 0, i8* %g, align 2
+ br label %if.end
+
+if.end: ; preds = %if.then, %entry
+ ret void
+}
diff --git a/llvm/test/CodeGen/MSP430/InstII.ll b/llvm/test/CodeGen/MSP430/InstII.ll
new file mode 100644
index 0000000..596d5b0
--- /dev/null
+++ b/llvm/test/CodeGen/MSP430/InstII.ll
@@ -0,0 +1,68 @@
+; RUN: llc -march=msp430 < %s | FileCheck %s
+target datalayout = "e-p:16:8:8-i8:8:8-i16:8:8-i32:8:8"
+target triple = "msp430-generic-generic"
+
+define void @rra8m(i8* %i) {
+entry:
+; CHECK-LABEL: rra8m:
+; CHECK: rra.b 2(r12)
+ %0 = getelementptr inbounds i8, i8* %i, i16 2
+ %1 = load i8, i8* %0, align 1
+ %shr = ashr i8 %1, 1
+ store i8 %shr, i8* %0, align 1
+ ret void
+}
+
+define void @rra16m(i16* %i) {
+entry:
+; CHECK-LABEL: rra16m:
+; CHECK: rra 4(r12)
+ %0 = getelementptr inbounds i16, i16* %i, i16 2
+ %1 = load i16, i16* %0, align 2
+ %shr = ashr i16 %1, 1
+ store i16 %shr, i16* %0, align 2
+ ret void
+}
+
+; TODO: `clrc; rrc.b 2(r12)` is expected
+define void @rrc8m(i8* %g) {
+entry:
+; CHECK-LABEL: rrc8m:
+; CHECK: mov.b 2(r12), r13
+; CHECK: clrc
+; CHECK: rrc.b r13
+; CHECK: mov.b r13, 2(r12)
+ %add.ptr = getelementptr inbounds i8, i8* %g, i16 2
+ %0 = load i8, i8* %add.ptr, align 1
+ %1 = lshr i8 %0, 1
+ store i8 %1, i8* %add.ptr, align 1
+ ret void
+}
+
+; TODO: `clrc; rrc 4(r12)` is expected
+define void @rrc16m(i16* %g) {
+entry:
+; CHECK-LABEL: rrc16m:
+; CHECK: mov 4(r12), r13
+; CHECK: clrc
+; CHECK: rrc r13
+; CHECK: mov r13, 4(r12)
+ %add.ptr = getelementptr inbounds i16, i16* %g, i16 2
+ %0 = load i16, i16* %add.ptr, align 2
+ %shr = lshr i16 %0, 1
+ store i16 %shr, i16* %add.ptr, align 2
+ ret void
+}
+
+define void @sxt16m(i16* %x) {
+entry:
+; CHECK-LABEL: sxt16m:
+; CHECK: sxt 4(r12)
+ %add.ptr = getelementptr inbounds i16, i16* %x, i16 2
+ %0 = bitcast i16* %add.ptr to i8*
+ %1 = load i8, i8* %0, align 1
+ %conv = sext i8 %1 to i16
+ store i16 %conv, i16* %add.ptr, align 2
+ ret void
+}
+
diff --git a/llvm/test/MC/Disassembler/MSP430/msp430.txt b/llvm/test/MC/Disassembler/MSP430/msp430.txt
index c7d6ff5..8e06f9d 100644
--- a/llvm/test/MC/Disassembler/MSP430/msp430.txt
+++ b/llvm/test/MC/Disassembler/MSP430/msp430.txt
@@ -19,9 +19,10 @@
0x1f 0x40 0x2a 0x00 # CHECK: mov 42, r15
0xb0 0x12 0x81 0x01 # CHECK: call #385
0x97 0x12 0x06 0x00 # CHECK: call 6(r7)
-0xa7 0xb2 0x02 0x00 # CHECK: bit #34, 2(r7)
+0xa7 0xb2 0x02 0x00 # CHECK: bit #4, 2(r7)
0xa9 0x57 0x08 0x00 # CHECK: add @r7, 8(r9)
0xb7 0xe7 0xfe 0xff # CHECK: xor @r7+, -2(r7)
0xbf 0x40 0x2a 0x00 0x0c 0x00 # CHECK: mov #42, 12(r15)
+0xb7 0xb0 0x22 0x00 0x02 0x00 # CHECK: bit #34, 2(r7)
0x9a 0xb9 0x10 0x00 0x08 0x00 # CHECK: bit 16(r9), 8(r10)
diff --git a/llvm/test/MC/MSP430/addrmode.s b/llvm/test/MC/MSP430/addrmode.s
index 46051c0..7e389b6 100644
--- a/llvm/test/MC/MSP430/addrmode.s
+++ b/llvm/test/MC/MSP430/addrmode.s
@@ -93,6 +93,8 @@
call r7
call 6(r7)
+ call @r7
+ call @r7+
call disp+6(r7)
call &disp
call disp
@@ -100,11 +102,61 @@
; CHECK: call r7 ; encoding: [0x87,0x12]
; CHECK: call 6(r7) ; encoding: [0x97,0x12,0x06,0x00]
+; CHECK: call @r7 ; encoding: [0xa7,0x12]
+; CHECK: call @r7+ ; encoding: [0xb7,0x12]
; CHECK: call disp+6(r7) ; encoding: [0x97,0x12,A,A]
; CHECK: call &disp ; encoding: [0x92,0x12,A,A]
; CHECK: call disp ; encoding: [0x90,0x12,A,A]
; CHECK: call #disp ; encoding: [0xb0,0x12,A,A]
+ rra r7 ; CHECK: rra r7 ; encoding: [0x07,0x11]
+ rra 2(r7) ; CHECK: rra 2(r7) ; encoding: [0x17,0x11,0x02,0x00]
+ rra @r7 ; CHECK: rra @r7 ; encoding: [0x27,0x11]
+ rra @r7+ ; CHECK: rra @r7+ ; encoding: [0x37,0x11]
+
+ rrc r7 ; CHECK: rrc r7 ; encoding: [0x07,0x10]
+ rrc 2(r7) ; CHECK: rrc 2(r7) ; encoding: [0x17,0x10,0x02,0x00]
+ rrc @r7 ; CHECK: rrc @r7 ; encoding: [0x27,0x10]
+ rrc @r7+ ; CHECK: rrc @r7+ ; encoding: [0x37,0x10]
+
+ swpb r7 ; CHECK: swpb r7 ; encoding: [0x87,0x10]
+ swpb 2(r7) ; CHECK: swpb 2(r7) ; encoding: [0x97,0x10,0x02,0x00]
+ swpb @r7 ; CHECK: swpb @r7 ; encoding: [0xa7,0x10]
+ swpb @r7+ ; CHECK: swpb @r7+ ; encoding: [0xb7,0x10]
+
+ sxt r7 ; CHECK: sxt r7 ; encoding: [0x87,0x11]
+ sxt 2(r7) ; CHECK: sxt 2(r7) ; encoding: [0x97,0x11,0x02,0x00]
+ sxt @r7 ; CHECK: sxt @r7 ; encoding: [0xa7,0x11]
+ sxt @r7+ ; CHECK: sxt @r7+ ; encoding: [0xb7,0x11]
+
+ cmp r5, r7 ; CHECK: cmp r5, r7 ; encoding: [0x07,0x95]
+ cmp 2(r5), r7 ; CHECK: cmp 2(r5), r7 ; encoding: [0x17,0x95,0x02,0x00]
+ cmp #-1, r7 ; CHECK: cmp #-1, r7 ; encoding: [0x37,0x93]
+ cmp #42, r7 ; CHECK: cmp #42, r7 ; encoding: [0x37,0x90,0x2a,0x00]
+ cmp @r5, r7 ; CHECK: cmp @r5, r7 ; encoding: [0x27,0x95]
+ cmp @r5+, r7 ; CHECK: cmp @r5+, r7 ; encoding: [0x37,0x95]
+
+ cmp r5, 2(r7) ; CHECK: cmp r5, 2(r7) ; encoding: [0x87,0x95,0x02,0x00]
+ cmp 2(r7), 2(r7) ; CHECK: cmp 2(r7), 2(r7) ; encoding: [0x97,0x97,0x02,0x00,0x02,0x00]
+ cmp #-1, 2(r7) ; CHECK: cmp #-1, 2(r7) ; encoding: [0xb7,0x93,0x02,0x00]
+ cmp #42, 2(r7) ; CHECK: cmp #42, 2(r7) ; encoding: [0xb7,0x90,0x2a,0x00,0x02,0x00]
+ cmp @r5, 2(r7) ; CHECK: cmp @r5, 2(r7) ; encoding: [0xa7,0x95,0x02,0x00]
+ cmp @r5+, 2(r7) ; CHECK: cmp @r5+, 2(r7) ; encoding: [0xb7,0x95,0x02,0x00]
+
+ bit r5, r7 ; CHECK: bit r5, r7 ; encoding: [0x07,0xb5]
+ bit 2(r5), r7 ; CHECK: bit 2(r5), r7 ; encoding: [0x17,0xb5,0x02,0x00]
+ bit #-1, r7 ; CHECK: bit #-1, r7 ; encoding: [0x37,0xb3]
+ bit #42, r7 ; CHECK: bit #42, r7 ; encoding: [0x37,0xb0,0x2a,0x00]
+ bit @r5, r7 ; CHECK: bit @r5, r7 ; encoding: [0x27,0xb5]
+ bit @r5+, r7 ; CHECK: bit @r5+, r7 ; encoding: [0x37,0xb5]
+
+ bit r5, 2(r7) ; CHECK: bit r5, 2(r7) ; encoding: [0x87,0xb5,0x02,0x00]
+ bit 2(r7), 2(r7) ; CHECK: bit 2(r7), 2(r7) ; encoding: [0x97,0xb7,0x02,0x00,0x02,0x00]
+ bit #-1, 2(r7) ; CHECK: bit #-1, 2(r7) ; encoding: [0xb7,0xb3,0x02,0x00]
+ bit #42, 2(r7) ; CHECK: bit #42, 2(r7) ; encoding: [0xb7,0xb0,0x2a,0x00,0x02,0x00]
+ bit @r5, 2(r7) ; CHECK: bit @r5, 2(r7) ; encoding: [0xa7,0xb5,0x02,0x00]
+ bit @r5+, 2(r7) ; CHECK: bit @r5+, 2(r7) ; encoding: [0xb7,0xb5,0x02,0x00]
+
disp:
.word 0xcafe
.word 0xbabe
diff --git a/llvm/test/MC/MSP430/const.s b/llvm/test/MC/MSP430/const.s
index f5cca10..dfaf32f 100644
--- a/llvm/test/MC/MSP430/const.s
+++ b/llvm/test/MC/MSP430/const.s
@@ -1,10 +1,13 @@
; RUN: llvm-mc -triple msp430 -show-encoding < %s | FileCheck %s
- mov #4, r15 ; CHECK: mov #4, r15 ; encoding: [0x2f,0x42]
- mov #8, r15 ; CHECK: mov #8, r15 ; encoding: [0x3f,0x42]
- mov #0, r15 ; CHECK: clr r15 ; encoding: [0x0f,0x43]
- mov #1, r15 ; CHECK: mov #1, r15 ; encoding: [0x1f,0x43]
- mov #2, r15 ; CHECK: mov #2, r15 ; encoding: [0x2f,0x43]
- mov #-1, r7 ; CHECK: mov #-1, r7 ; encoding: [0x37,0x43]
- push #8 ; CHECK: push #8 ; encoding: [0x32,0x12]
- push #42 ; CHECK: push #42 ; encoding: [0x30,0x12,0x2a,0x00]
+ mov #4, r15 ; CHECK: mov #4, r15 ; encoding: [0x2f,0x42]
+ mov #8, r15 ; CHECK: mov #8, r15 ; encoding: [0x3f,0x42]
+ mov #0, r15 ; CHECK: clr r15 ; encoding: [0x0f,0x43]
+ mov #1, r15 ; CHECK: mov #1, r15 ; encoding: [0x1f,0x43]
+ mov #2, r15 ; CHECK: mov #2, r15 ; encoding: [0x2f,0x43]
+ mov #-1, r7 ; CHECK: mov #-1, r7 ; encoding: [0x37,0x43]
+
+ push #8 ; CHECK: push #8 ; encoding: [0x32,0x12]
+ push #42 ; CHECK: push #42 ; encoding: [0x30,0x12,0x2a,0x00]
+
+ bit #1, 0(r7) ; CHECK: bit #1, 0(r7) ; encoding: [0x97,0xb3,0x00,0x00]