[MSP430] Add missing instruction forms
* Add missing mm, [r|m]n, [r|m]p instruction forms.
* Fix bit16mc instruction.
Patch by Kristina Bessonova!
Differential Revision: https://reviews.llvm.org/D56546
llvm-svn: 350902
diff --git a/llvm/test/CodeGen/MSP430/Inst16mm.ll b/llvm/test/CodeGen/MSP430/Inst16mm.ll
index 21fab42..af00a18 100644
--- a/llvm/test/CodeGen/MSP430/Inst16mm.ll
+++ b/llvm/test/CodeGen/MSP430/Inst16mm.ll
@@ -67,3 +67,22 @@
; CHECK-DAG: mov 2(r1), 6(r1)
; CHECK-DAG: mov 0(r1), 4(r1)
}
+
+define void @cmp(i16* %g, i16* %i) {
+entry:
+; CHECK-LABEL: cmp:
+; CHECK: cmp 8(r12), 4(r13)
+ %add.ptr = getelementptr inbounds i16, i16* %g, i16 4
+ %0 = load i16, i16* %add.ptr, align 2
+ %add.ptr1 = getelementptr inbounds i16, i16* %i, i16 2
+ %1 = load i16, i16* %add.ptr1, align 2
+ %cmp = icmp sgt i16 %0, %1
+ br i1 %cmp, label %if.then, label %if.end
+
+if.then: ; preds = %entry
+ store i16 0, i16* %g, align 2
+ br label %if.end
+
+if.end: ; preds = %if.then, %entry
+ ret void
+}
diff --git a/llvm/test/CodeGen/MSP430/Inst8mm.ll b/llvm/test/CodeGen/MSP430/Inst8mm.ll
index b9848dc..5709728 100644
--- a/llvm/test/CodeGen/MSP430/Inst8mm.ll
+++ b/llvm/test/CodeGen/MSP430/Inst8mm.ll
@@ -53,3 +53,21 @@
ret void
}
+define void @cmp(i8* %g, i8* %i) {
+entry:
+; CHECK-LABEL: cmp:
+; CHECK: cmp.b 4(r12), 2(r13)
+ %add.ptr = getelementptr inbounds i8, i8* %g, i16 4
+ %0 = load i8, i8* %add.ptr, align 1
+ %add.ptr1 = getelementptr inbounds i8, i8* %i, i16 2
+ %1 = load i8, i8* %add.ptr1, align 1
+ %cmp = icmp sgt i8 %0, %1
+ br i1 %cmp, label %if.then, label %if.end
+
+if.then: ; preds = %entry
+ store i8 0, i8* %g, align 2
+ br label %if.end
+
+if.end: ; preds = %if.then, %entry
+ ret void
+}
diff --git a/llvm/test/CodeGen/MSP430/InstII.ll b/llvm/test/CodeGen/MSP430/InstII.ll
new file mode 100644
index 0000000..596d5b0
--- /dev/null
+++ b/llvm/test/CodeGen/MSP430/InstII.ll
@@ -0,0 +1,68 @@
+; RUN: llc -march=msp430 < %s | FileCheck %s
+target datalayout = "e-p:16:8:8-i8:8:8-i16:8:8-i32:8:8"
+target triple = "msp430-generic-generic"
+
+define void @rra8m(i8* %i) {
+entry:
+; CHECK-LABEL: rra8m:
+; CHECK: rra.b 2(r12)
+ %0 = getelementptr inbounds i8, i8* %i, i16 2
+ %1 = load i8, i8* %0, align 1
+ %shr = ashr i8 %1, 1
+ store i8 %shr, i8* %0, align 1
+ ret void
+}
+
+define void @rra16m(i16* %i) {
+entry:
+; CHECK-LABEL: rra16m:
+; CHECK: rra 4(r12)
+ %0 = getelementptr inbounds i16, i16* %i, i16 2
+ %1 = load i16, i16* %0, align 2
+ %shr = ashr i16 %1, 1
+ store i16 %shr, i16* %0, align 2
+ ret void
+}
+
+; TODO: `clrc; rrc.b 2(r12)` is expected
+define void @rrc8m(i8* %g) {
+entry:
+; CHECK-LABEL: rrc8m:
+; CHECK: mov.b 2(r12), r13
+; CHECK: clrc
+; CHECK: rrc.b r13
+; CHECK: mov.b r13, 2(r12)
+ %add.ptr = getelementptr inbounds i8, i8* %g, i16 2
+ %0 = load i8, i8* %add.ptr, align 1
+ %1 = lshr i8 %0, 1
+ store i8 %1, i8* %add.ptr, align 1
+ ret void
+}
+
+; TODO: `clrc; rrc 4(r12)` is expected
+define void @rrc16m(i16* %g) {
+entry:
+; CHECK-LABEL: rrc16m:
+; CHECK: mov 4(r12), r13
+; CHECK: clrc
+; CHECK: rrc r13
+; CHECK: mov r13, 4(r12)
+ %add.ptr = getelementptr inbounds i16, i16* %g, i16 2
+ %0 = load i16, i16* %add.ptr, align 2
+ %shr = lshr i16 %0, 1
+ store i16 %shr, i16* %add.ptr, align 2
+ ret void
+}
+
+define void @sxt16m(i16* %x) {
+entry:
+; CHECK-LABEL: sxt16m:
+; CHECK: sxt 4(r12)
+ %add.ptr = getelementptr inbounds i16, i16* %x, i16 2
+ %0 = bitcast i16* %add.ptr to i8*
+ %1 = load i8, i8* %0, align 1
+ %conv = sext i8 %1 to i16
+ store i16 %conv, i16* %add.ptr, align 2
+ ret void
+}
+