[OPENMP] Simplify codegen for non-offloading code.
Simplified and generalized codegen for non-offloading part that works if
offloading is failed or condition of the `if` clause is `false`.
llvm-svn: 314670
diff --git a/clang/test/OpenMP/target_codegen.cpp b/clang/test/OpenMP/target_codegen.cpp
index 6ed4e59..153f19d 100644
--- a/clang/test/OpenMP/target_codegen.cpp
+++ b/clang/test/OpenMP/target_codegen.cpp
@@ -93,9 +93,7 @@
TT<long long, char> d;
// CHECK: [[RET:%.+]] = call i32 @__tgt_target(i32 -1, i8* @{{[^,]+}}, i32 0, i8** null, i8** null, i[[SZ]]* null, i32* null)
- // CHECK: store i32 [[RET]], i32* [[RHV:%.+]], align 4
- // CHECK: [[RET2:%.+]] = load i32, i32* [[RHV]], align 4
- // CHECK-NEXT: [[ERROR:%.+]] = icmp ne i32 [[RET2]], 0
+ // CHECK-NEXT: [[ERROR:%.+]] = icmp ne i32 [[RET]], 0
// CHECK-NEXT: br i1 [[ERROR]], label %[[FAIL:[^,]+]], label %[[END:[^,]+]]
// CHECK: [[FAIL]]
// CHECK: call void [[HVT0:@.+]]()
@@ -105,10 +103,6 @@
{
}
- // CHECK: store i32 0, i32* [[RHV:%.+]], align 4
- // CHECK: store i32 -1, i32* [[RHV]], align 4
- // CHECK: [[RET2:%.+]] = load i32, i32* [[RHV]], align 4
- // CHECK-NEXT: [[ERROR:%.+]] = icmp ne i32 [[RET2]], 0
// CHECK: call void [[HVT1:@.+]](i[[SZ]] {{[^,]+}})
#pragma omp target if(0) firstprivate(global)
{
@@ -125,9 +119,7 @@
// CHECK-DAG: store i[[SZ]] [[BP0:%[^,]+]], i[[SZ]]* [[CBPADDR0]]
// CHECK-DAG: store i[[SZ]] [[P0:%[^,]+]], i[[SZ]]* [[CPADDR0]]
- // CHECK: store i32 [[RET]], i32* [[RHV:%.+]], align 4
- // CHECK: [[RET2:%.+]] = load i32, i32* [[RHV]], align 4
- // CHECK-NEXT: [[ERROR:%.+]] = icmp ne i32 [[RET2]], 0
+ // CHECK: [[ERROR:%.+]] = icmp ne i32 [[RET]], 0
// CHECK-NEXT: br i1 [[ERROR]], label %[[FAIL:[^,]+]], label %[[END:[^,]+]]
// CHECK: [[FAIL]]
// CHECK: call void [[HVT2:@.+]](i[[SZ]] {{[^,]+}})
@@ -158,21 +150,18 @@
// CHECK-DAG: [[CPADDR1:%.+]] = bitcast i8** [[PADDR1]] to i[[SZ]]*
// CHECK-DAG: store i[[SZ]] [[BP1:%[^,]+]], i[[SZ]]* [[CBPADDR1]]
// CHECK-DAG: store i[[SZ]] [[P1:%[^,]+]], i[[SZ]]* [[CPADDR1]]
- // CHECK: store i32 [[RET]], i32* [[RHV:%.+]], align 4
- // CHECK-NEXT: br label %[[IFEND:.+]]
-
- // CHECK: [[IFELSE]]
- // CHECK: store i32 -1, i32* [[RHV]], align 4
- // CHECK-NEXT: br label %[[IFEND:.+]]
-
- // CHECK: [[IFEND]]
- // CHECK: [[RET2:%.+]] = load i32, i32* [[RHV]], align 4
- // CHECK: [[ERROR:%.+]] = icmp ne i32 [[RET2]], 0
+ // CHECK: [[ERROR:%.+]] = icmp ne i32 [[RET]], 0
// CHECK-NEXT: br i1 [[ERROR]], label %[[FAIL:.+]], label %[[END:[^,]+]]
// CHECK: [[FAIL]]
// CHECK: call void [[HVT3:@.+]]({{[^,]+}}, {{[^,]+}})
// CHECK-NEXT: br label %[[END]]
// CHECK: [[END]]
+ // CHECK-NEXT: br label %[[IFEND:.+]]
+ // CHECK: [[IFELSE]]
+ // CHECK: call void [[HVT3]]({{[^,]+}}, {{[^,]+}})
+ // CHECK-NEXT: br label %[[IFEND]]
+
+ // CHECK: [[IFEND]]
#pragma omp target if(n>10)
{
a += 1;
@@ -285,15 +274,18 @@
// CHECK-DAG: store [[TT]]* %{{.+}}, [[TT]]** [[CPADDR8]]
// CHECK-DAG: store i[[SZ]] {{12|16}}, i[[SZ]]* [[SADDR8]]
- // CHECK: store i32 [[RET]], i32* [[RHV:%.+]], align 4
- // CHECK: [[RET2:%.+]] = load i32, i32* [[RHV]], align 4
- // CHECK-NEXT: [[ERROR:%.+]] = icmp ne i32 [[RET2]], 0
- // CHECK-NEXT: br i1 [[ERROR]], label %[[FAIL:[^,]+]], label %[[END:[^,]+]]
-
+ // CHECK: [[ERROR:%.+]] = icmp ne i32 [[RET]], 0
+ // CHECK-NEXT: br i1 [[ERROR]], label %[[FAIL:.+]], label %[[END:[^,]+]]
// CHECK: [[FAIL]]
// CHECK: call void [[HVT4:@.+]]({{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}})
// CHECK-NEXT: br label %[[END]]
// CHECK: [[END]]
+ // CHECK-NEXT: br label %[[IFEND:.+]]
+ // CHECK: [[IFELSE]]
+ // CHECK: call void [[HVT4]]({{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}})
+ // CHECK-NEXT: br label %[[IFEND]]
+
+ // CHECK: [[IFEND]]
#pragma omp target if(n>20)
{
a += 1;
@@ -521,15 +513,18 @@
// CHECK-DAG: store i16* %{{.+}}, i16** [[CPADDR4]]
// CHECK-DAG: store i[[SZ]] [[CSIZE]], i[[SZ]]* [[SADDR4]]
-// CHECK: store i32 [[RET]], i32* [[RHV:%.+]], align 4
-// CHECK: [[RET2:%.+]] = load i32, i32* [[RHV]], align 4
-// CHECK-NEXT: [[ERROR:%.+]] = icmp ne i32 [[RET2]], 0
-// CHECK-NEXT: br i1 [[ERROR]], label %[[FAIL:[^,]+]], label %[[END:[^,]+]]
-
+// CHECK: [[ERROR:%.+]] = icmp ne i32 [[RET]], 0
+// CHECK-NEXT: br i1 [[ERROR]], label %[[FAIL:.+]], label %[[END:[^,]+]]
// CHECK: [[FAIL]]
// CHECK: call void [[HVT7:@.+]]({{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}})
// CHECK-NEXT: br label %[[END]]
// CHECK: [[END]]
+// CHECK-NEXT: br label %[[IFEND:.+]]
+// CHECK: [[IFELSE]]
+// CHECK: call void [[HVT7]]({{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}})
+// CHECK-NEXT: br label %[[IFEND]]
+
+// CHECK: [[IFEND]]
//
// CHECK: define {{.*}}[[FSTATIC]]
@@ -569,21 +564,18 @@
// CHECK-DAG: store [10 x i32]* [[VAL3:%[^,]+]], [10 x i32]** [[CBPADDR3]]
// CHECK-DAG: store [10 x i32]* [[VAL3]], [10 x i32]** [[CPADDR3]]
-// CHECK: store i32 [[RET]], i32* [[RHV:%.+]], align 4
-// CHECK-NEXT: br label %[[IFEND:.+]]
-
-// CHECK: [[IFELSE]]
-// CHECK: store i32 -1, i32* [[RHV]], align 4
-// CHECK-NEXT: br label %[[IFEND:.+]]
-
-// CHECK: [[IFEND]]
-// CHECK: [[RET2:%.+]] = load i32, i32* [[RHV]], align 4
-// CHECK: [[ERROR:%.+]] = icmp ne i32 [[RET2]], 0
+// CHECK: [[ERROR:%.+]] = icmp ne i32 [[RET]], 0
// CHECK-NEXT: br i1 [[ERROR]], label %[[FAIL:.+]], label %[[END:[^,]+]]
// CHECK: [[FAIL]]
// CHECK: call void [[HVT6:@.+]]({{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}})
// CHECK-NEXT: br label %[[END]]
// CHECK: [[END]]
+// CHECK-NEXT: br label %[[IFEND:.+]]
+// CHECK: [[IFELSE]]
+// CHECK: call void [[HVT6]]({{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}})
+// CHECK-NEXT: br label %[[IFEND]]
+
+// CHECK: [[IFEND]]
//
// CHECK: define {{.*}}[[FTEMPLATE]]
@@ -616,22 +608,18 @@
// CHECK-DAG: store [10 x i32]* [[VAL2:%[^,]+]], [10 x i32]** [[CBPADDR2]]
// CHECK-DAG: store [10 x i32]* [[VAL2]], [10 x i32]** [[CPADDR2]]
-// CHECK: store i32 [[RET]], i32* [[RHV:%.+]], align 4
-// CHECK-NEXT: br label %[[IFEND:.+]]
-
-// CHECK: [[IFELSE]]
-// CHECK: store i32 -1, i32* [[RHV]], align 4
-// CHECK-NEXT: br label %[[IFEND:.+]]
-
-// CHECK: [[IFEND]]
-// CHECK: [[RET2:%.+]] = load i32, i32* [[RHV]], align 4
-// CHECK: [[ERROR:%.+]] = icmp ne i32 [[RET2]], 0
+// CHECK: [[ERROR:%.+]] = icmp ne i32 [[RET]], 0
// CHECK-NEXT: br i1 [[ERROR]], label %[[FAIL:.+]], label %[[END:[^,]+]]
// CHECK: [[FAIL]]
// CHECK: call void [[HVT5:@.+]]({{[^,]+}}, {{[^,]+}}, {{[^,]+}})
// CHECK-NEXT: br label %[[END]]
// CHECK: [[END]]
+// CHECK-NEXT: br label %[[IFEND:.+]]
+// CHECK: [[IFELSE]]
+// CHECK: call void [[HVT5]]({{[^,]+}}, {{[^,]+}}, {{[^,]+}})
+// CHECK-NEXT: br label %[[IFEND]]
+// CHECK: [[IFEND]]
// Check that the offloading functions are emitted and that the arguments are