[x86][icelake]VAES introduction
an icelake promotion of AES
Differential Revision: https://reviews.llvm.org/D40078
llvm-svn: 318740
diff --git a/llvm/lib/Target/X86/X86.td b/llvm/lib/Target/X86/X86.td
index 62aab84..5c7bb00 100644
--- a/llvm/lib/Target/X86/X86.td
+++ b/llvm/lib/Target/X86/X86.td
@@ -172,6 +172,9 @@
def FeatureAES : SubtargetFeature<"aes", "HasAES", "true",
"Enable AES instructions",
[FeatureSSE2]>;
+def FeatureVAES : SubtargetFeature<"vaes", "HasVAES", "true",
+ "Promote selected AES instructions to AVX512/AVX registers",
+ [FeatureAVX, FeatureAES]>;
def FeatureTBM : SubtargetFeature<"tbm", "HasTBM", "true",
"Enable TBM instructions">;
def FeatureLWP : SubtargetFeature<"lwp", "HasLWP", "true",
diff --git a/llvm/lib/Target/X86/X86InstrAVX512.td b/llvm/lib/Target/X86/X86InstrAVX512.td
index 95dd782..964e495 100644
--- a/llvm/lib/Target/X86/X86InstrAVX512.td
+++ b/llvm/lib/Target/X86/X86InstrAVX512.td
@@ -10013,3 +10013,30 @@
defm : AVX512_scalar_math_f64_patterns<fsub, "SUB">;
defm : AVX512_scalar_math_f64_patterns<fmul, "MUL">;
defm : AVX512_scalar_math_f64_patterns<fdiv, "DIV">;
+
+//===----------------------------------------------------------------------===//
+// AES instructions
+//===----------------------------------------------------------------------===//
+multiclass avx512_vaes<bits<8> Op, string OpStr, string IntPrefix> {
+ let Predicates = [HasVLX, HasVAES] in {
+ defm Z128 : AESI_binop_rm_int<Op, OpStr,
+ !cast<Intrinsic>(IntPrefix),
+ loadv2i64, 0, VR128X, i128mem>,
+ EVEX_4V, EVEX_CD8<64, CD8VF>, EVEX_V128, VEX_WIG;
+ defm Z256 : AESI_binop_rm_int<Op, OpStr,
+ !cast<Intrinsic>(IntPrefix##"_256"),
+ loadv4i64, 0, VR256X, i256mem>,
+ EVEX_4V, EVEX_CD8<64, CD8VF>, EVEX_V256, VEX_WIG;
+ }
+ let Predicates = [HasAVX512, HasVAES] in
+ defm Z : AESI_binop_rm_int<Op, OpStr,
+ !cast<Intrinsic>(IntPrefix##"_512"),
+ loadv8i64, 0, VR512, i512mem>,
+ EVEX_4V, EVEX_CD8<64, CD8VF>, EVEX_V512, VEX_WIG;
+}
+
+defm VAESENC : avx512_vaes<0xDC, "vaesenc", "int_x86_aesni_aesenc">;
+defm VAESENCLAST : avx512_vaes<0xDD, "vaesenclast", "int_x86_aesni_aesenclast">;
+defm VAESDEC : avx512_vaes<0xDE, "vaesdec", "int_x86_aesni_aesdec">;
+defm VAESDECLAST : avx512_vaes<0xDF, "vaesdeclast", "int_x86_aesni_aesdeclast">;
+
diff --git a/llvm/lib/Target/X86/X86InstrInfo.td b/llvm/lib/Target/X86/X86InstrInfo.td
index f00caa1..c869825 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.td
+++ b/llvm/lib/Target/X86/X86InstrInfo.td
@@ -835,6 +835,8 @@
def HasPOPCNT : Predicate<"Subtarget->hasPOPCNT()">;
def HasAES : Predicate<"Subtarget->hasAES()">;
+def HasVAES : Predicate<"Subtarget->hasVAES()">;
+def NoVLX_Or_NoVAES : Predicate<"!Subtarget->hasVLX() || !Subtarget->hasVAES()">;
def HasFXSR : Predicate<"Subtarget->hasFXSR()">;
def HasXSAVE : Predicate<"Subtarget->hasXSAVE()">;
def HasXSAVEOPT : Predicate<"Subtarget->hasXSAVEOPT()">;
diff --git a/llvm/lib/Target/X86/X86InstrSSE.td b/llvm/lib/Target/X86/X86InstrSSE.td
index 7e20951..a0b370e 100644
--- a/llvm/lib/Target/X86/X86InstrSSE.td
+++ b/llvm/lib/Target/X86/X86InstrSSE.td
@@ -7129,46 +7129,60 @@
// AES-NI Instructions
//===----------------------------------------------------------------------===//
-multiclass AESI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId128,
- PatFrag ld_frag, bit Is2Addr = 1> {
- def rr : AES8I<opc, MRMSrcReg, (outs VR128:$dst),
- (ins VR128:$src1, VR128:$src2),
- !if(Is2Addr,
- !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
- !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
- [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
- Sched<[WriteAESDecEnc]>;
- def rm : AES8I<opc, MRMSrcMem, (outs VR128:$dst),
- (ins VR128:$src1, i128mem:$src2),
- !if(Is2Addr,
- !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
- !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
- [(set VR128:$dst,
- (IntId128 VR128:$src1, (ld_frag addr:$src2)))]>,
- Sched<[WriteAESDecEncLd, ReadAfterLd]>;
+multiclass AESI_binop_rm_int<bits<8> opc, string OpcodeStr,
+ Intrinsic IntId, PatFrag ld_frag,
+ bit Is2Addr = 0, RegisterClass RC = VR128,
+ X86MemOperand MemOp = i128mem> {
+ let AsmString = OpcodeStr##
+ !if(Is2Addr, "\t{$src2, $dst|$dst, $src2}",
+ "\t{$src2, $src1, $dst|$dst, $src1, $src2}") in {
+ def rr : AES8I<opc, MRMSrcReg, (outs RC:$dst),
+ (ins RC:$src1, RC:$src2), "",
+ [(set RC:$dst, (IntId RC:$src1, RC:$src2))]>,
+ Sched<[WriteAESDecEnc]>;
+ def rm : AES8I<opc, MRMSrcMem, (outs RC:$dst),
+ (ins RC:$src1, MemOp:$src2), "",
+ [(set RC:$dst, (IntId RC:$src1, (ld_frag addr:$src2)))]>,
+ Sched<[WriteAESDecEncLd, ReadAfterLd]>;
+ }
}
// Perform One Round of an AES Encryption/Decryption Flow
-let Predicates = [HasAVX, HasAES] in {
+let Predicates = [HasAVX, NoVLX_Or_NoVAES, HasAES] in {
defm VAESENC : AESI_binop_rm_int<0xDC, "vaesenc",
- int_x86_aesni_aesenc, loadv2i64, 0>, VEX_4V, VEX_WIG;
+ int_x86_aesni_aesenc, loadv2i64>, VEX_4V, VEX_WIG;
defm VAESENCLAST : AESI_binop_rm_int<0xDD, "vaesenclast",
- int_x86_aesni_aesenclast, loadv2i64, 0>, VEX_4V, VEX_WIG;
+ int_x86_aesni_aesenclast, loadv2i64>, VEX_4V, VEX_WIG;
defm VAESDEC : AESI_binop_rm_int<0xDE, "vaesdec",
- int_x86_aesni_aesdec, loadv2i64, 0>, VEX_4V, VEX_WIG;
+ int_x86_aesni_aesdec, loadv2i64>, VEX_4V, VEX_WIG;
defm VAESDECLAST : AESI_binop_rm_int<0xDF, "vaesdeclast",
- int_x86_aesni_aesdeclast, loadv2i64, 0>, VEX_4V, VEX_WIG;
+ int_x86_aesni_aesdeclast, loadv2i64>, VEX_4V, VEX_WIG;
+}
+
+let Predicates = [NoVLX, HasVAES] in {
+ defm VAESENCY : AESI_binop_rm_int<0xDC, "vaesenc",
+ int_x86_aesni_aesenc_256, loadv4i64, 0, VR256,
+ i256mem>, VEX_4V, VEX_L, VEX_WIG;
+ defm VAESENCLASTY : AESI_binop_rm_int<0xDD, "vaesenclast",
+ int_x86_aesni_aesenclast_256, loadv4i64, 0, VR256,
+ i256mem>, VEX_4V, VEX_L, VEX_WIG;
+ defm VAESDECY : AESI_binop_rm_int<0xDE, "vaesdec",
+ int_x86_aesni_aesdec_256, loadv4i64, 0, VR256,
+ i256mem>, VEX_4V, VEX_L, VEX_WIG;
+ defm VAESDECLASTY : AESI_binop_rm_int<0xDF, "vaesdeclast",
+ int_x86_aesni_aesdeclast_256, loadv4i64, 0, VR256,
+ i256mem>, VEX_4V, VEX_L, VEX_WIG;
}
let Constraints = "$src1 = $dst" in {
defm AESENC : AESI_binop_rm_int<0xDC, "aesenc",
- int_x86_aesni_aesenc, memopv2i64>;
+ int_x86_aesni_aesenc, memopv2i64, 1>;
defm AESENCLAST : AESI_binop_rm_int<0xDD, "aesenclast",
- int_x86_aesni_aesenclast, memopv2i64>;
+ int_x86_aesni_aesenclast, memopv2i64, 1>;
defm AESDEC : AESI_binop_rm_int<0xDE, "aesdec",
- int_x86_aesni_aesdec, memopv2i64>;
+ int_x86_aesni_aesdec, memopv2i64, 1>;
defm AESDECLAST : AESI_binop_rm_int<0xDF, "aesdeclast",
- int_x86_aesni_aesdeclast, memopv2i64>;
+ int_x86_aesni_aesdeclast, memopv2i64, 1>;
}
// Perform the AES InvMixColumn Transformation
diff --git a/llvm/lib/Target/X86/X86Subtarget.cpp b/llvm/lib/Target/X86/X86Subtarget.cpp
index 1d1a78f..a4581e1 100644
--- a/llvm/lib/Target/X86/X86Subtarget.cpp
+++ b/llvm/lib/Target/X86/X86Subtarget.cpp
@@ -292,6 +292,7 @@
HasPOPCNT = false;
HasSSE4A = false;
HasAES = false;
+ HasVAES = false;
HasFXSR = false;
HasXSAVE = false;
HasXSAVEOPT = false;
diff --git a/llvm/lib/Target/X86/X86Subtarget.h b/llvm/lib/Target/X86/X86Subtarget.h
index 0b1eddc..3f0657b 100644
--- a/llvm/lib/Target/X86/X86Subtarget.h
+++ b/llvm/lib/Target/X86/X86Subtarget.h
@@ -107,6 +107,7 @@
/// Target has AES instructions
bool HasAES;
+ bool HasVAES;
/// Target has FXSAVE/FXRESTOR instructions
bool HasFXSR;
@@ -457,6 +458,7 @@
bool has3DNowA() const { return X863DNowLevel >= ThreeDNowA; }
bool hasPOPCNT() const { return HasPOPCNT; }
bool hasAES() const { return HasAES; }
+ bool hasVAES() const { return HasVAES; }
bool hasFXSR() const { return HasFXSR; }
bool hasXSAVE() const { return HasXSAVE; }
bool hasXSAVEOPT() const { return HasXSAVEOPT; }