Remove definitions of double word shift plus 32 instructions. Assembler or
direct-object emitter should emit the appropriate shift instruction depending
on the shift amount.
llvm-svn: 146893
diff --git a/llvm/test/CodeGen/Mips/mips64ext.ll b/llvm/test/CodeGen/Mips/mips64ext.ll
index 33af0d8..ae6078b 100644
--- a/llvm/test/CodeGen/Mips/mips64ext.ll
+++ b/llvm/test/CodeGen/Mips/mips64ext.ll
@@ -3,8 +3,8 @@
define i64 @zext64_32(i32 %a) nounwind readnone {
entry:
; CHECK: addiu $[[R0:[0-9]+]], ${{[0-9]+}}, 2
-; CHECK: dsll32 $[[R1:[0-9]+]], $[[R0]], 0
-; CHECK: dsrl32 ${{[0-9]+}}, $[[R1]], 0
+; CHECK: dsll $[[R1:[0-9]+]], $[[R0]], 32
+; CHECK: dsrl ${{[0-9]+}}, $[[R1]], 32
%add = add i32 %a, 2
%conv = zext i32 %add to i64
ret i64 %conv
diff --git a/llvm/test/CodeGen/Mips/mips64shift.ll b/llvm/test/CodeGen/Mips/mips64shift.ll
index cc5e508..45d1c95 100644
--- a/llvm/test/CodeGen/Mips/mips64shift.ll
+++ b/llvm/test/CodeGen/Mips/mips64shift.ll
@@ -44,21 +44,21 @@
define i64 @f6(i64 %a0) nounwind readnone {
entry:
-; CHECK: dsll32 ${{[0-9]+}}, ${{[0-9]+}}, 8
+; CHECK: dsll ${{[0-9]+}}, ${{[0-9]+}}, 40
%shl = shl i64 %a0, 40
ret i64 %shl
}
define i64 @f7(i64 %a0) nounwind readnone {
entry:
-; CHECK: dsra32 ${{[0-9]+}}, ${{[0-9]+}}, 8
+; CHECK: dsra ${{[0-9]+}}, ${{[0-9]+}}, 40
%shr = ashr i64 %a0, 40
ret i64 %shr
}
define i64 @f8(i64 %a0) nounwind readnone {
entry:
-; CHECK: dsrl32 ${{[0-9]+}}, ${{[0-9]+}}, 8
+; CHECK: dsrl ${{[0-9]+}}, ${{[0-9]+}}, 40
%shr = lshr i64 %a0, 40
ret i64 %shr
}
@@ -94,7 +94,7 @@
define i64 @f12(i64 %a0) nounwind readnone {
entry:
-; CHECK: drotr32 ${{[0-9]+}}, ${{[0-9]+}}, 22
+; CHECK: drotr ${{[0-9]+}}, ${{[0-9]+}}, 54
%shl = shl i64 %a0, 10
%shr = lshr i64 %a0, 54
%or = or i64 %shl, %shr