commit 2a30d7889fc54c8a74d73b79be3dd030bac41b06
author Craig Topper <craig.topper@gmail.com> Wed Jun 18 05:05:13 2014 +0000
committer Craig Topper <craig.topper@gmail.com> Wed Jun 18 05:05:13 2014 +0000
tree 2e930ab7dd12150c6d0809b193b24f5618beeb2c
parent f29276edb7b9c85c9f521eb3e301259bee17aa33

Replace some assert(0)'s with llvm_unreachable.

llvm-svn: 211141

llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp

diff --git a/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp b/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
index 79075b0..9df0054 100644
--- a/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
+++ b/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
@@ -330,7 +330,7 @@
     unsigned Reg = Op.getReg();
     unsigned regIdx = 0;
     switch (Op.Reg.Kind) {
-    default: assert(0 && "Unexpected register kind!");
+    default: llvm_unreachable("Unexpected register kind!");
     case rk_FloatReg:
       regIdx = Reg - Sparc::F0;
       if (regIdx % 4 || regIdx > 31)