ARM: do not generate BLX instructions on Cortex-M CPUs.
Particularly on MachO, we were generating "blx _dest" instructions on M-class
CPUs, which don't actually exist. They happen to get fixed up by the linker
into valid "bl _dest" instructions (which is why such a massive issue has
remained largely undetected), but we shouldn't rely on that.
llvm-svn: 214959
diff --git a/llvm/test/CodeGen/ARM/darwin-eabi.ll b/llvm/test/CodeGen/ARM/darwin-eabi.ll
index f2cde71..45ba3c0 100644
--- a/llvm/test/CodeGen/ARM/darwin-eabi.ll
+++ b/llvm/test/CodeGen/ARM/darwin-eabi.ll
@@ -7,7 +7,7 @@
%sum = fadd float %lhs, %rhs
ret float %sum
; CHECK-M3-LABEL: float_op:
-; CHECK-M3: blx ___addsf3
+; CHECK-M3: bl ___addsf3
; CHECK-M4-LABEL: float_op:
; CHECK-M4: vadd.f32
@@ -17,8 +17,8 @@
%sum = fadd double %lhs, %rhs
ret double %sum
; CHECK-M3-LABEL: double_op:
-; CHECK-M3: blx ___adddf3
+; CHECK-M3: bl ___adddf3
; CHECK-M4-LABEL: double_op:
-; CHECK-M4: blx ___adddf3
+; CHECK-M4: bl ___adddf3
}