commit 2a480599bb688dc9bb4fc24b60958c15968a3b85
author Krzysztof Parzyszek <kparzysz@codeaurora.org> Tue Jul 26 20:30:30 2016 +0000
committer Krzysztof Parzyszek <kparzysz@codeaurora.org> Tue Jul 26 20:30:30 2016 +0000
tree 9099ea96dd42db51342491762624af2a9b5d1aad
parent ad2b717f2c8fcc279cf13aa51349012c3710c987

[Hexagon] Post-increment loads/stores enhancements

- Generate vector post-increment stores more aggressively.
- Predicate post-increment and vector stores in early if-conversion.

llvm-svn: 276800

llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp

diff --git a/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp b/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
index ba98b27..ef87959 100644
--- a/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
@@ -326,7 +326,13 @@
 // TODO: MI->isIndirectBranch() and IsRegisterJump(MI)
 // Returns true if an instruction can be promoted to .new predicate or
 // new-value store.
-bool HexagonPacketizerList::isNewifiable(const MachineInstr* MI) {
+bool HexagonPacketizerList::isNewifiable(const MachineInstr* MI,
+      const TargetRegisterClass *NewRC) {
+  // Vector stores can be predicated, and can be new-value stores, but
+  // they cannot be predicated on a .new predicate value.
+  if (NewRC == &Hexagon::PredRegsRegClass)
+    if (HII->isV60VectorInstruction(MI) && MI->mayStore())
+      return false;
   return HII->isCondInst(MI) || MI->isReturn() || HII->mayBeNewStore(MI);
 }
 
@@ -767,7 +773,7 @@
   if (HII->isDotNewInst(MI) && !HII->mayBeNewStore(MI))
     return false;
 
-  if (!isNewifiable(MI))
+  if (!isNewifiable(MI, RC))
     return false;
 
   const MachineInstr *PI = PacketSU->getInstr();