| commit | 2a57b357a3a0de2202a3fb0272d2648a205bcdfa | [log] [tgz] |
|---|---|---|
| author | Sjoerd Meijer <sjoerd.meijer@arm.com> | Fri Jul 06 08:03:12 2018 +0000 |
| committer | Sjoerd Meijer <sjoerd.meijer@arm.com> | Fri Jul 06 08:03:12 2018 +0000 |
| tree | 7a78591803955adc522b572bfac72a8ce8e58e15 | |
| parent | be4c2933a2c370d292122fc2187d75436aeaea83 [diff] |
[AArch64][ARM] Armv8.4-A: Trace synchronization barrier instruction This adds the Armv8.4-A Trace synchronization barrier (TSB) instruction. Differential Revision: https://reviews.llvm.org/D48918 llvm-svn: 336418