[PPC] Properly update register save area offsets
The variables MinGPR/MinG8R were not updated properly when resetting the
offsets, which in the included testcase lead to saving the CR register
in the same location as R30.
This fixes another issue reported in PR26519.
Differential Revision: https://reviews.llvm.org/D33017
llvm-svn: 303257
diff --git a/llvm/test/CodeGen/PowerPC/save-cr-ppc32svr4.ll b/llvm/test/CodeGen/PowerPC/save-cr-ppc32svr4.ll
new file mode 100644
index 0000000..9fabca1
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/save-cr-ppc32svr4.ll
@@ -0,0 +1,46 @@
+; RUN: llc -march=ppc32 -relocation-model pic < %s | FileCheck %s
+;
+; Make sure that the CR register is saved correctly on PPC32/SVR4.
+
+; CHECK-LABEL: fred:
+; CHECK: stwu 1, -32(1)
+; CHECK: stw 31, 28(1)
+; CHECK: mr 31, 1
+; CHECK: stw 30, 24(1)
+; CHECK: mfcr [[CR:[0-9]+]]
+; CHECK: stw [[CR]], 20(31)
+
+target datalayout = "E-m:e-p:32:32-i64:64-n32"
+target triple = "powerpc-unknown-freebsd"
+
+; Function Attrs: norecurse nounwind readnone sspstrong
+define i64 @fred(double %a0) local_unnamed_addr #0 {
+b1:
+ %v2 = fcmp olt double %a0, 0x43E0000000000000
+ br i1 %v2, label %b3, label %b7
+
+b3: ; preds = %b1
+ %v4 = fcmp olt double %a0, 0xC3E0000000000000
+ %v5 = fptosi double %a0 to i64
+ %v6 = select i1 %v4, i64 -9223372036854775808, i64 %v5
+ br label %b14
+
+b7: ; preds = %b1
+ %v8 = fcmp olt double %a0, 0x43F0000000000000
+ br i1 %v8, label %b9, label %b11
+
+b9: ; preds = %b7
+ %v10 = fptoui double %a0 to i64
+ br label %b14
+
+b11: ; preds = %b7
+ %v12 = fcmp ogt double %a0, 0.000000e+00
+ %v13 = sext i1 %v12 to i64
+ br label %b14
+
+b14: ; preds = %b11, %b9, %b3
+ %v15 = phi i64 [ %v6, %b3 ], [ %v10, %b9 ], [ %v13, %b11 ]
+ ret i64 %v15
+}
+
+attributes #0 = { norecurse nounwind readnone sspstrong "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "stack-protector-buffer-size"="8" "target-cpu"="ppc" }