[IRTranslator] Add G_SUB opcode.
This commit adds a generic SUB opcode to global-isel.
llvm-svn: 276308
diff --git a/llvm/include/llvm/Target/GenericOpcodes.td b/llvm/include/llvm/Target/GenericOpcodes.td
index 1adc38b..889523e 100644
--- a/llvm/include/llvm/Target/GenericOpcodes.td
+++ b/llvm/include/llvm/Target/GenericOpcodes.td
@@ -23,6 +23,14 @@
let isCommutable = 1;
}
+// Generic subtraction.
+def G_SUB : Instruction {
+ let OutOperandList = (outs unknown:$dst);
+ let InOperandList = (ins unknown:$src1, unknown:$src2);
+ let hasSideEffects = 0;
+ let isCommutable = 0;
+}
+
// Generic bitwise and.
def G_AND : Instruction {
let OutOperandList = (outs unknown:$dst);
diff --git a/llvm/include/llvm/Target/TargetOpcodes.def b/llvm/include/llvm/Target/TargetOpcodes.def
index 97ce0f8..b17a949 100644
--- a/llvm/include/llvm/Target/TargetOpcodes.def
+++ b/llvm/include/llvm/Target/TargetOpcodes.def
@@ -159,6 +159,9 @@
HANDLE_TARGET_OPCODE(G_ADD)
HANDLE_TARGET_OPCODE_MARKER(PRE_ISEL_GENERIC_OPCODE_START, G_ADD)
+/// Generic SUB instruction. This is an integer sub.
+HANDLE_TARGET_OPCODE(G_SUB)
+
/// Generic Bitwise-AND instruction.
HANDLE_TARGET_OPCODE(G_AND)
diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
index 145f2e2..e017b49 100644
--- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
@@ -105,6 +105,8 @@
// Arithmetic operations.
case Instruction::Add:
return translateBinaryOp(TargetOpcode::G_ADD, Inst);
+ case Instruction::Sub:
+ return translateBinaryOp(TargetOpcode::G_SUB, Inst);
// Bitwise operations.
case Instruction::And:
return translateBinaryOp(TargetOpcode::G_AND, Inst);
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
index 15fa017..721c98d 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
@@ -84,3 +84,26 @@
%res = and i32 %arg1, %arg2
ret i32 %res
}
+
+; Tests for sub.
+; CHECK: name: subi64
+; CHECK: [[ARG1:%[0-9]+]](64) = COPY %x0
+; CHECK-NEXT: [[ARG2:%[0-9]+]](64) = COPY %x1
+; CHECK-NEXT: [[RES:%[0-9]+]](64) = G_SUB s64 [[ARG1]], [[ARG2]]
+; CHECK-NEXT: %x0 = COPY [[RES]]
+; CHECK-NEXT: RET_ReallyLR implicit %x0
+define i64 @subi64(i64 %arg1, i64 %arg2) {
+ %res = sub i64 %arg1, %arg2
+ ret i64 %res
+}
+
+; CHECK: name: subi32
+; CHECK: [[ARG1:%[0-9]+]](32) = COPY %w0
+; CHECK-NEXT: [[ARG2:%[0-9]+]](32) = COPY %w1
+; CHECK-NEXT: [[RES:%[0-9]+]](32) = G_SUB s32 [[ARG1]], [[ARG2]]
+; CHECK-NEXT: %w0 = COPY [[RES]]
+; CHECK-NEXT: RET_ReallyLR implicit %w0
+define i32 @subi32(i32 %arg1, i32 %arg2) {
+ %res = sub i32 %arg1, %arg2
+ ret i32 %res
+}