commit 2bea69bf6503ffc9f3cde9a52b5dac1a25e94e1c
author Daniel Sanders <daniel_l_sanders@apple.com> Thu Aug 01 23:27:28 2019 +0000
committer Daniel Sanders <daniel_l_sanders@apple.com> Thu Aug 01 23:27:28 2019 +0000
tree 91dc8f6a4635d24a9c93d1e5080a67b8baae69f8
parent 9debb024d44db54b9453459d3bd98d28c20a163f

Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Register as started by r367614. NFC

llvm-svn: 367633

llvm/lib/Target/Mips/MipsInstructionSelector.cpp

diff --git a/llvm/lib/Target/Mips/MipsInstructionSelector.cpp b/llvm/lib/Target/Mips/MipsInstructionSelector.cpp
index 2ec12fd..2cb2e94 100644
--- a/llvm/lib/Target/Mips/MipsInstructionSelector.cpp
+++ b/llvm/lib/Target/Mips/MipsInstructionSelector.cpp
@@ -84,7 +84,7 @@
 bool MipsInstructionSelector::selectCopy(MachineInstr &I,
                                          MachineRegisterInfo &MRI) const {
   Register DstReg = I.getOperand(0).getReg();
-  if (TargetRegisterInfo::isPhysicalRegister(DstReg))
+  if (Register::isPhysicalRegister(DstReg))
     return true;
 
   const RegisterBank *RegBank = RBI.getRegBank(DstReg, MRI, TRI);
@@ -289,7 +289,7 @@
     const unsigned OpSize = MRI.getType(DestReg).getSizeInBits();
 
     const TargetRegisterClass *DefRC = nullptr;
-    if (TargetRegisterInfo::isPhysicalRegister(DestReg))
+    if (Register::isPhysicalRegister(DestReg))
       DefRC = TRI.getRegClass(DestReg);
     else
       DefRC = getRegClassForTypeOnBank(OpSize,