[RISCV][NFC] Convert some MachineBaiscBlock::iterator(MI) to MI.getIterator()
llvm-svn: 355864
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 60041da..9b4193e 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -813,8 +813,8 @@
F->insert(I, IfFalseMBB);
F->insert(I, TailMBB);
// Move all remaining instructions to TailMBB.
- TailMBB->splice(TailMBB->begin(), HeadMBB,
- std::next(MachineBasicBlock::iterator(MI)), HeadMBB->end());
+ TailMBB->splice(TailMBB->begin(), HeadMBB, std::next(MI.getIterator()),
+ HeadMBB->end());
// Update machine-CFG edges by transferring all successors of the current
// block to the new block which will contain the Phi node for the select.
TailMBB->transferSuccessorsAndUpdatePHIs(HeadMBB);
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index ddb976b..dc63c51 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -382,8 +382,8 @@
.addMBB(&DestBB, RISCVII::MO_LO);
RS->enterBasicBlockEnd(MBB);
- unsigned Scav = RS->scavengeRegisterBackwards(
- RISCV::GPRRegClass, MachineBasicBlock::iterator(LuiMI), false, 0);
+ unsigned Scav = RS->scavengeRegisterBackwards(RISCV::GPRRegClass,
+ LuiMI.getIterator(), false, 0);
MRI.replaceRegWith(ScratchReg, Scav);
MRI.clearVirtRegs();
RS->setRegUsed(Scav);