commit 2c6c84e52c452e3d4a94ecf0e85c1cb526603580
author Alex Bradbury <asb@lowrisc.org> Mon Mar 11 20:43:29 2019 +0000
committer Alex Bradbury <asb@lowrisc.org> Mon Mar 11 20:43:29 2019 +0000
tree 6e6bc0029bbda681e2333c9055a08ad1f07d5a74
parent 7bc83564357eb805c90b7d941103732ddfa221bb

[RISCV][NFC] Convert some MachineBaiscBlock::iterator(MI) to MI.getIterator()

llvm-svn: 355864

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index ddb976b..dc63c51 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -382,8 +382,8 @@
       .addMBB(&DestBB, RISCVII::MO_LO);
 
   RS->enterBasicBlockEnd(MBB);
-  unsigned Scav = RS->scavengeRegisterBackwards(
-      RISCV::GPRRegClass, MachineBasicBlock::iterator(LuiMI), false, 0);
+  unsigned Scav = RS->scavengeRegisterBackwards(RISCV::GPRRegClass,
+                                                LuiMI.getIterator(), false, 0);
   MRI.replaceRegWith(ScratchReg, Scav);
   MRI.clearVirtRegs();
   RS->setRegUsed(Scav);