[ARM] Unify handling of M-Class system registers
This patch cleans up and fixes issues in the M-Class system register handling:
1. It defines the system registers and the encoding (SYSm values) in one place:
a new ARMSystemRegister.td using SearchableTable, thereby removing the
hand-coded values which existed in multiple places.
2. Some system registers e.g. BASEPRI_MAX_NS which do not exist were being allowed!
Ref: ARMv6/7/8M architecture reference manual.
Reviewed by: @t.p.northover, @olist01, @john.brawn
Differential Revision: https://reviews.llvm.org/D35209
llvm-svn: 308456
diff --git a/llvm/lib/Target/ARM/Utils/ARMBaseInfo.cpp b/llvm/lib/Target/ARM/Utils/ARMBaseInfo.cpp
new file mode 100644
index 0000000..08c2afc4
--- /dev/null
+++ b/llvm/lib/Target/ARM/Utils/ARMBaseInfo.cpp
@@ -0,0 +1,44 @@
+//===-- ARMBaseInfo.cpp - ARM Base encoding information------------===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file provides basic encoding and assembly information for ARM.
+//
+//===----------------------------------------------------------------------===//
+#include "ARMBaseInfo.h"
+#include "llvm/ADT/ArrayRef.h"
+#include "llvm/ADT/SmallVector.h"
+#include "llvm/ADT/StringExtras.h"
+#include "llvm/Support/Regex.h"
+
+using namespace llvm;
+namespace llvm {
+ namespace ARMSysReg {
+
+// lookup system register using 12-bit SYSm value.
+// Note: the search is uniqued using M1 mask
+const MClassSysReg *lookupMClassSysRegBy12bitSYSmValue(unsigned SYSm) {
+ return lookupMClassSysRegByM1Encoding12(SYSm);
+}
+
+// returns APSR with _<bits> qualifier.
+// Note: ARMv7-M deprecates using MSR APSR without a _<bits> qualifier
+const MClassSysReg *lookupMClassSysRegAPSRNonDeprecated(unsigned SYSm) {
+ return lookupMClassSysRegByM2M3Encoding8((1<<9)|(SYSm & 0xFF));
+}
+
+// lookup system registers using 8-bit SYSm value
+const MClassSysReg *lookupMClassSysRegBy8bitSYSmValue(unsigned SYSm) {
+ return ARMSysReg::lookupMClassSysRegByM2M3Encoding8((1<<8)|(SYSm & 0xFF));
+}
+
+#define GET_MCLASSSYSREG_IMPL
+#include "ARMGenSystemRegister.inc"
+
+ }
+}
diff --git a/llvm/lib/Target/ARM/Utils/ARMBaseInfo.h b/llvm/lib/Target/ARM/Utils/ARMBaseInfo.h
new file mode 100644
index 0000000..dc8c83c
--- /dev/null
+++ b/llvm/lib/Target/ARM/Utils/ARMBaseInfo.h
@@ -0,0 +1,64 @@
+//===-- ARMBaseInfo.h - Top level definitions for ARM ---*- C++ -*-===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file contains small standalone helper functions and enum definitions for
+// the ARM target useful for the compiler back-end and the MC libraries.
+// As such, it deliberately does not include references to LLVM core
+// code gen types, passes, etc..
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_ARM_UTILS_ARMBASEINFO_H
+#define LLVM_LIB_TARGET_ARM_UTILS_ARMBASEINFO_H
+
+#include "llvm/ADT/StringSwitch.h"
+#include "llvm/Support/ErrorHandling.h"
+#include "llvm/MC/SubtargetFeature.h"
+#include "MCTargetDesc/ARMMCTargetDesc.h"
+
+namespace llvm {
+
+namespace ARMSysReg {
+ struct MClassSysReg {
+ const char *Name;
+ uint16_t M1Encoding12;
+ uint16_t M2M3Encoding8;
+ uint16_t Encoding;
+ FeatureBitset FeaturesRequired;
+
+ // return true if FeaturesRequired are all present in ActiveFeatures
+ bool hasRequiredFeatures(FeatureBitset ActiveFeatures) const {
+ return (FeaturesRequired & ActiveFeatures) == FeaturesRequired;
+ }
+
+ // returns true if TestFeatures are all present in FeaturesRequired
+ bool isInRequiredFeatures(FeatureBitset TestFeatures) const {
+ return (FeaturesRequired & TestFeatures) == TestFeatures;
+ }
+ };
+
+ #define GET_MCLASSSYSREG_DECL
+ #include "ARMGenSystemRegister.inc"
+
+ // lookup system register using 12-bit SYSm value.
+ // Note: the search is uniqued using M1 mask
+ const MClassSysReg *lookupMClassSysRegBy12bitSYSmValue(unsigned SYSm);
+
+ // returns APSR with _<bits> qualifier.
+ // Note: ARMv7-M deprecates using MSR APSR without a _<bits> qualifier
+ const MClassSysReg *lookupMClassSysRegAPSRNonDeprecated(unsigned SYSm);
+
+ // lookup system registers using 8-bit SYSm value
+ const MClassSysReg *lookupMClassSysRegBy8bitSYSmValue(unsigned SYSm);
+
+} // end namespace ARMSysReg
+
+} // end namespace llvm
+
+#endif // LLVM_LIB_TARGET_ARM_UTILS_ARMBASEINFO_H
diff --git a/llvm/lib/Target/ARM/Utils/CMakeLists.txt b/llvm/lib/Target/ARM/Utils/CMakeLists.txt
new file mode 100644
index 0000000..61bfe0a
--- /dev/null
+++ b/llvm/lib/Target/ARM/Utils/CMakeLists.txt
@@ -0,0 +1,3 @@
+add_llvm_library(LLVMARMUtils
+ ARMBaseInfo.cpp
+ )
diff --git a/llvm/lib/Target/ARM/Utils/LLVMBuild.txt b/llvm/lib/Target/ARM/Utils/LLVMBuild.txt
new file mode 100644
index 0000000..bbbaef6
--- /dev/null
+++ b/llvm/lib/Target/ARM/Utils/LLVMBuild.txt
@@ -0,0 +1,24 @@
+;===- ./lib/Target/ARM/Utils/LLVMBuild.txt ----------------*- Conf -*--===;
+;
+; The LLVM Compiler Infrastructure
+;
+; This file is distributed under the University of Illinois Open Source
+; License. See LICENSE.TXT for details.
+;
+;===------------------------------------------------------------------------===;
+;
+; This is an LLVMBuild description file for the components in this subdirectory.
+;
+; For more information on the LLVMBuild system, please see:
+;
+; http://llvm.org/docs/LLVMBuild.html
+;
+;===------------------------------------------------------------------------===;
+
+[component_0]
+type = Library
+name = ARMUtils
+parent = ARM
+required_libraries = Support
+add_to_library_groups = ARM
+