[X86] Handle COPYs of physregs better (regalloc hints)
Enable enableMultipleCopyHints() on X86.
Original Patch by @jonpa:
While enabling the mischeduler for SystemZ, it was discovered that for some reason a test needed one extra seemingly needless COPY (test/CodeGen/SystemZ/call-03.ll). The handling for that is resulted in this patch, which improves the register coalescing by providing not just one copy hint, but a sorted list of copy hints. On SystemZ, this gives ~12500 less register moves on SPEC, as well as marginally less spilling.
Instead of improving just the SystemZ backend, the improvement has been implemented in common-code (calculateSpillWeightAndHint(). This gives a lot of test failures, but since this should be a general improvement I hope that the involved targets will help and review the test updates.
Differential Revision: https://reviews.llvm.org/D38128
llvm-svn: 342578
diff --git a/llvm/test/CodeGen/X86/bitcast-int-to-vector-bool.ll b/llvm/test/CodeGen/X86/bitcast-int-to-vector-bool.ll
index c1b1140..1acc834 100644
--- a/llvm/test/CodeGen/X86/bitcast-int-to-vector-bool.ll
+++ b/llvm/test/CodeGen/X86/bitcast-int-to-vector-bool.ll
@@ -193,8 +193,8 @@
define <32 x i1> @bitcast_i32_32i1(i32 %a0) {
; SSE2-SSSE3-LABEL: bitcast_i32_32i1:
; SSE2-SSSE3: # %bb.0:
-; SSE2-SSSE3-NEXT: movl %esi, (%rdi)
; SSE2-SSSE3-NEXT: movq %rdi, %rax
+; SSE2-SSSE3-NEXT: movl %esi, (%rdi)
; SSE2-SSSE3-NEXT: retq
;
; AVX1-LABEL: bitcast_i32_32i1:
@@ -250,14 +250,14 @@
define <64 x i1> @bitcast_i64_64i1(i64 %a0) {
; SSE2-SSSE3-LABEL: bitcast_i64_64i1:
; SSE2-SSSE3: # %bb.0:
-; SSE2-SSSE3-NEXT: movq %rsi, (%rdi)
; SSE2-SSSE3-NEXT: movq %rdi, %rax
+; SSE2-SSSE3-NEXT: movq %rsi, (%rdi)
; SSE2-SSSE3-NEXT: retq
;
; AVX12-LABEL: bitcast_i64_64i1:
; AVX12: # %bb.0:
-; AVX12-NEXT: movq %rsi, (%rdi)
; AVX12-NEXT: movq %rdi, %rax
+; AVX12-NEXT: movq %rsi, (%rdi)
; AVX12-NEXT: retq
;
; AVX512-LABEL: bitcast_i64_64i1: