commit 2d550d19b321837aac647ec9e8c5b6f26f682b17
author Luis Marques <luismarques@lowrisc.org> Tue Sep 17 10:52:09 2019 +0000
committer Luis Marques <luismarques@lowrisc.org> Tue Sep 17 10:52:09 2019 +0000
tree 7f0ad38a58fa4517934ec23827d367b92cb284fa
parent 0b10da7cc786b36b8bf553222ac27a4170770110

Revert Patch from Phabricator

This reverts r372092 (git commit e38695a0255c9e7b53639f349f8101bae1ce5c04)

llvm-svn: 372104

llvm/test/CodeGen/RISCV/float-select-fcmp.ll

diff --git a/llvm/test/CodeGen/RISCV/float-select-fcmp.ll b/llvm/test/CodeGen/RISCV/float-select-fcmp.ll
index 142e4f8..ec81c53 100644
--- a/llvm/test/CodeGen/RISCV/float-select-fcmp.ll
+++ b/llvm/test/CodeGen/RISCV/float-select-fcmp.ll
@@ -240,14 +240,14 @@
 define float @select_fcmp_ueq(float %a, float %b) nounwind {
 ; RV32IF-LABEL: select_fcmp_ueq:
 ; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fmv.w.x ft1, a1
 ; RV32IF-NEXT:    fmv.w.x ft0, a0
-; RV32IF-NEXT:    feq.s a0, ft0, ft1
-; RV32IF-NEXT:    feq.s a1, ft1, ft1
-; RV32IF-NEXT:    feq.s a2, ft0, ft0
-; RV32IF-NEXT:    and a1, a2, a1
-; RV32IF-NEXT:    seqz a1, a1
-; RV32IF-NEXT:    or a0, a0, a1
+; RV32IF-NEXT:    fmv.w.x ft1, a1
+; RV32IF-NEXT:    feq.s a0, ft1, ft1
+; RV32IF-NEXT:    feq.s a1, ft0, ft0
+; RV32IF-NEXT:    and a0, a1, a0
+; RV32IF-NEXT:    seqz a0, a0
+; RV32IF-NEXT:    feq.s a1, ft0, ft1
+; RV32IF-NEXT:    or a0, a1, a0
 ; RV32IF-NEXT:    bnez a0, .LBB8_2
 ; RV32IF-NEXT:  # %bb.1:
 ; RV32IF-NEXT:    fmv.s ft0, ft1
@@ -257,14 +257,14 @@
 ;
 ; RV64IF-LABEL: select_fcmp_ueq:
 ; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fmv.w.x ft1, a1
 ; RV64IF-NEXT:    fmv.w.x ft0, a0
-; RV64IF-NEXT:    feq.s a0, ft0, ft1
-; RV64IF-NEXT:    feq.s a1, ft1, ft1
-; RV64IF-NEXT:    feq.s a2, ft0, ft0
-; RV64IF-NEXT:    and a1, a2, a1
-; RV64IF-NEXT:    seqz a1, a1
-; RV64IF-NEXT:    or a0, a0, a1
+; RV64IF-NEXT:    fmv.w.x ft1, a1
+; RV64IF-NEXT:    feq.s a0, ft1, ft1
+; RV64IF-NEXT:    feq.s a1, ft0, ft0
+; RV64IF-NEXT:    and a0, a1, a0
+; RV64IF-NEXT:    seqz a0, a0
+; RV64IF-NEXT:    feq.s a1, ft0, ft1
+; RV64IF-NEXT:    or a0, a1, a0
 ; RV64IF-NEXT:    bnez a0, .LBB8_2
 ; RV64IF-NEXT:  # %bb.1:
 ; RV64IF-NEXT:    fmv.s ft0, ft1
@@ -486,24 +486,24 @@
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    fmv.w.x ft0, a1
 ; RV32IF-NEXT:    fmv.w.x ft1, a0
-; RV32IF-NEXT:    feq.s a1, ft1, ft0
-; RV32IF-NEXT:    mv a0, a2
-; RV32IF-NEXT:    bnez a1, .LBB16_2
+; RV32IF-NEXT:    feq.s a0, ft1, ft0
+; RV32IF-NEXT:    bnez a0, .LBB16_2
 ; RV32IF-NEXT:  # %bb.1:
-; RV32IF-NEXT:    mv a0, a3
+; RV32IF-NEXT:    mv a2, a3
 ; RV32IF-NEXT:  .LBB16_2:
+; RV32IF-NEXT:    mv a0, a2
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: i32_select_fcmp_oeq:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fmv.w.x ft0, a1
 ; RV64IF-NEXT:    fmv.w.x ft1, a0
-; RV64IF-NEXT:    feq.s a1, ft1, ft0
-; RV64IF-NEXT:    mv a0, a2
-; RV64IF-NEXT:    bnez a1, .LBB16_2
+; RV64IF-NEXT:    feq.s a0, ft1, ft0
+; RV64IF-NEXT:    bnez a0, .LBB16_2
 ; RV64IF-NEXT:  # %bb.1:
-; RV64IF-NEXT:    mv a0, a3
+; RV64IF-NEXT:    mv a2, a3
 ; RV64IF-NEXT:  .LBB16_2:
+; RV64IF-NEXT:    mv a0, a2
 ; RV64IF-NEXT:    ret
   %1 = fcmp oeq float %a, %b
   %2 = select i1 %1, i32 %c, i32 %d