| commit | 2d8c289b4bd0d244e4743a41729184b90486517f | [log] [tgz] |
|---|---|---|
| author | Matt Arsenault <Matthew.Arsenault@amd.com> | Tue Nov 01 20:42:24 2016 +0000 |
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | Tue Nov 01 20:42:24 2016 +0000 |
| tree | fb44b0b9fc49d1ac86ea87bcd8b34e62f65a0b16 | |
| parent | 306b62b4aed8631b585fe0ee4f0532ca7ac53c37 [diff] |
AMDGPU: Workaround for instruction size with literals Instructions with a 32-bit base encoding with an optional 32-bit literal encoded after them report their size as 4 for the disassembler. Consider these when computing the MachineInstr size. This fixes problems caused by size estimate consistency in BranchRelaxation. llvm-svn: 285743