[mips][microMIPS] Implement SLT, SLTI, SLTIU, SLTU microMIPS32r6 instructions
Differential Revision: https://reviews.llvm.org/D19906
llvm-svn: 276397
diff --git a/llvm/test/CodeGen/Mips/brconlt.ll b/llvm/test/CodeGen/Mips/brconlt.ll
index 487018c..65f6c34 100644
--- a/llvm/test/CodeGen/Mips/brconlt.ll
+++ b/llvm/test/CodeGen/Mips/brconlt.ll
@@ -1,4 +1,5 @@
; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc -march=mips -mattr=micromips -mcpu=mips32r6 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MM32R6
@i = global i32 5, align 4
@j = global i32 10, align 4
@@ -12,9 +13,10 @@
%cmp = icmp slt i32 %0, %1
br i1 %cmp, label %if.end, label %if.then
-; 16: slt ${{[0-9]+}}, ${{[0-9]+}}
-; 16: btnez $[[LABEL:[0-9A-Ba-b_]+]]
-; 16: $[[LABEL]]:
+; 16: slt ${{[0-9]+}}, ${{[0-9]+}}
+; MM32R6: slt ${{[0-9]+}}, ${{[0-9]+}}
+; 16: btnez $[[LABEL:[0-9A-Ba-b_]+]]
+; 16: $[[LABEL]]:
if.then: ; preds = %entry
store i32 1, i32* @result, align 4
diff --git a/llvm/test/CodeGen/Mips/setcc-se.ll b/llvm/test/CodeGen/Mips/setcc-se.ll
index 99071c4..b6c6b81 100644
--- a/llvm/test/CodeGen/Mips/setcc-se.ll
+++ b/llvm/test/CodeGen/Mips/setcc-se.ll
@@ -1,9 +1,12 @@
; RUN: llc -march=mipsel < %s | FileCheck %s
+; RUN: llc -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic < %s -asm-show-inst | FileCheck %s -check-prefix=MMR6
@g1 = external global i32
; CHECK-LABEL: seteq0:
-; CHECK: sltiu ${{[0-9]+}}, $4, 1
+; CHECK: sltiu ${{[0-9]+}}, $4, 1
+; MMR6: sltiu ${{[0-9]+}}, $4, 1
+; MMR6: <MCInst #{{[0-9]+}} SLTiu_MM
define i32 @seteq0(i32 %a) {
entry:
@@ -13,7 +16,9 @@
}
; CHECK-LABEL: setne0:
-; CHECK: sltu ${{[0-9]+}}, $zero, $4
+; CHECK: sltu ${{[0-9]+}}, $zero, $4
+; MMR6: sltu ${{[0-9]+}}, $zero, $4
+; MMR6: <MCInst #{{[0-9]+}} SLTu_MM
define i32 @setne0(i32 %a) {
entry:
@@ -23,8 +28,10 @@
}
; CHECK-LABEL: slti_beq0:
-; CHECK: slti $[[R0:[0-9]+]], $4, -32768
-; CHECK: beqz $[[R0]]
+; CHECK: slti $[[R0:[0-9]+]], $4, -32768
+; MMR6: slti $[[R0:[0-9]+]], $4, -32768
+; MMR6: <MCInst #{{[0-9]+}} SLTi_MM
+; CHECK: beqz $[[R0]]
define void @slti_beq0(i32 %a) {
entry:
@@ -40,7 +47,9 @@
}
; CHECK-LABEL: slti_beq1:
-; CHECK: slt ${{[0-9]+}}
+; CHECK: slt ${{[0-9]+}}
+; MMR6: slt ${{[0-9]+}}
+; MMR6: <MCInst #{{[0-9]+}} SLT_MM
define void @slti_beq1(i32 %a) {
entry:
@@ -56,8 +65,10 @@
}
; CHECK-LABEL: slti_beq2:
-; CHECK: slti $[[R0:[0-9]+]], $4, 32767
-; CHECK: beqz $[[R0]]
+; CHECK: slti $[[R0:[0-9]+]], $4, 32767
+; MMR6: slti $[[R0:[0-9]+]], $4, 32767
+; MMR6: <MCInst #{{[0-9]+}} SLTi_MM
+; CHECK: beqz $[[R0]]
define void @slti_beq2(i32 %a) {
entry:
@@ -73,7 +84,9 @@
}
; CHECK-LABEL: slti_beq3:
-; CHECK: slt ${{[0-9]+}}
+; CHECK: slt ${{[0-9]+}}
+; MMR6: slt ${{[0-9]+}}
+; MMR6: <MCInst #{{[0-9]+}} SLT_MM
define void @slti_beq3(i32 %a) {
entry:
@@ -89,8 +102,10 @@
}
; CHECK-LABEL: sltiu_beq0:
-; CHECK: sltiu $[[R0:[0-9]+]], $4, 32767
-; CHECK: beqz $[[R0]]
+; CHECK: sltiu $[[R0:[0-9]+]], $4, 32767
+; MMR6: sltiu $[[R0:[0-9]+]], $4, 32767
+; MMR6: <MCInst #{{[0-9]+}} SLTiu_MM
+; CHECK: beqz $[[R0]]
define void @sltiu_beq0(i32 %a) {
entry:
@@ -106,7 +121,9 @@
}
; CHECK-LABEL: sltiu_beq1:
-; CHECK: sltu ${{[0-9]+}}
+; CHECK: sltu ${{[0-9]+}}
+; MMR6: sltu ${{[0-9]+}}
+; MMR6: <MCInst #{{[0-9]+}} SLTu_MM
define void @sltiu_beq1(i32 %a) {
entry:
@@ -122,8 +139,10 @@
}
; CHECK-LABEL: sltiu_beq2:
-; CHECK: sltiu $[[R0:[0-9]+]], $4, -32768
-; CHECK: beqz $[[R0]]
+; CHECK: sltiu $[[R0:[0-9]+]], $4, -32768
+; MMR6: sltiu $[[R0:[0-9]+]], $4, -32768
+; MMR6: <MCInst #{{[0-9]+}} SLTiu_MM
+; CHECK: beqz $[[R0]]
define void @sltiu_beq2(i32 %a) {
entry:
@@ -139,7 +158,9 @@
}
; CHECK-LABEL: sltiu_beq3:
-; CHECK: sltu ${{[0-9]+}}
+; CHECK: sltu ${{[0-9]+}}
+; MMR6: sltu ${{[0-9]+}}
+; MMR6: <MCInst #{{[0-9]+}} SLTu_MM
define void @sltiu_beq3(i32 %a) {
entry:
diff --git a/llvm/test/CodeGen/Mips/seteq.ll b/llvm/test/CodeGen/Mips/seteq.ll
index 76f9bb3..0f0850f 100644
--- a/llvm/test/CodeGen/Mips/seteq.ll
+++ b/llvm/test/CodeGen/Mips/seteq.ll
@@ -1,4 +1,5 @@
; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6
@i = global i32 1, align 4
@j = global i32 10, align 4
@@ -13,9 +14,10 @@
%cmp = icmp eq i32 %0, %1
%conv = zext i1 %cmp to i32
store i32 %conv, i32* @r1, align 4
-; 16: xor $[[REGISTER:[0-9A-Ba-b_]+]], ${{[0-9]+}}
-; 16: sltiu $[[REGISTER:[0-9A-Ba-b_]+]], 1
-; 16: move ${{[0-9]+}}, $24
+; 16: xor $[[REGISTER:[0-9A-Ba-b_]+]], ${{[0-9]+}}
+; 16: sltiu $[[REGISTER:[0-9A-Ba-b_]+]], 1
+; MMR6: sltiu ${{[0-9]+}}, ${{[0-9]+}}, 1
+; 16: move ${{[0-9]+}}, $24
ret void
}
diff --git a/llvm/test/CodeGen/Mips/seteqz.ll b/llvm/test/CodeGen/Mips/seteqz.ll
index 368e85c..e611145 100644
--- a/llvm/test/CodeGen/Mips/seteqz.ll
+++ b/llvm/test/CodeGen/Mips/seteqz.ll
@@ -1,4 +1,5 @@
; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6
@i = global i32 0, align 4
@j = global i32 99, align 4
@@ -11,14 +12,16 @@
%cmp = icmp eq i32 %0, 0
%conv = zext i1 %cmp to i32
store i32 %conv, i32* @r1, align 4
-; 16: sltiu ${{[0-9]+}}, 1
-; 16: move ${{[0-9]+}}, $24
+; 16: sltiu ${{[0-9]+}}, 1
+; MMR6: sltiu ${{[0-9]+}}, ${{[0-9]+}}, 1
+; 16: move ${{[0-9]+}}, $24
%1 = load i32, i32* @j, align 4
%cmp1 = icmp eq i32 %1, 99
%conv2 = zext i1 %cmp1 to i32
store i32 %conv2, i32* @r2, align 4
-; 16: xor $[[REGISTER:[0-9A-Ba-b_]+]], ${{[0-9]+}}
-; 16: sltiu $[[REGISTER:[0-9A-Ba-b_]+]], 1
-; 16: move ${{[0-9]+}}, $24
+; 16: xor $[[REGISTER:[0-9A-Ba-b_]+]], ${{[0-9]+}}
+; 16: sltiu $[[REGISTER:[0-9A-Ba-b_]+]], 1
+; MMR6: sltiu ${{[0-9]+}}, ${{[0-9]+}}, 1
+; 16: move ${{[0-9]+}}, $24
ret void
}
diff --git a/llvm/test/CodeGen/Mips/setge.ll b/llvm/test/CodeGen/Mips/setge.ll
index af69d7b..0809b6f 100644
--- a/llvm/test/CodeGen/Mips/setge.ll
+++ b/llvm/test/CodeGen/Mips/setge.ll
@@ -1,4 +1,5 @@
; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6
@j = global i32 -5, align 4
@k = global i32 10, align 4
@@ -16,9 +17,10 @@
%cmp = icmp sge i32 %0, %1
%conv = zext i1 %cmp to i32
store i32 %conv, i32* @r1, align 4
-; 16: slt ${{[0-9]+}}, ${{[0-9]+}}
-; 16: move $[[REGISTER:[0-9]+]], $24
-; 16: xor $[[REGISTER]], ${{[0-9]+}}
+; 16: slt ${{[0-9]+}}, ${{[0-9]+}}
+; MMR6: slt ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}}
+; 16: move $[[REGISTER:[0-9]+]], $24
+; 16: xor $[[REGISTER]], ${{[0-9]+}}
%2 = load i32, i32* @m, align 4
%cmp1 = icmp sge i32 %0, %2
%conv2 = zext i1 %cmp1 to i32
diff --git a/llvm/test/CodeGen/Mips/setgek.ll b/llvm/test/CodeGen/Mips/setgek.ll
index d6eee1f..99d8eb2 100644
--- a/llvm/test/CodeGen/Mips/setgek.ll
+++ b/llvm/test/CodeGen/Mips/setgek.ll
@@ -1,4 +1,5 @@
; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6
@k = global i32 10, align 4
@r1 = common global i32 0, align 4
@@ -11,8 +12,9 @@
%cmp = icmp sgt i32 %0, -32769
%conv = zext i1 %cmp to i32
store i32 %conv, i32* @r1, align 4
-; 16: slti ${{[0-9]+}}, -32768
-; 16: move ${{[0-9]+}}, $24
-; 16: xor ${{[0-9]+}}, ${{[0-9]+}}
+; 16: slti ${{[0-9]+}}, -32768
+; MMR6: slt ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}}
+; 16: move ${{[0-9]+}}, $24
+; 16: xor ${{[0-9]+}}, ${{[0-9]+}}
ret void
}
diff --git a/llvm/test/CodeGen/Mips/setle.ll b/llvm/test/CodeGen/Mips/setle.ll
index f7d2505..31e2d62 100644
--- a/llvm/test/CodeGen/Mips/setle.ll
+++ b/llvm/test/CodeGen/Mips/setle.ll
@@ -1,4 +1,5 @@
; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6
@j = global i32 -5, align 4
@k = global i32 10, align 4
@@ -15,9 +16,10 @@
%cmp = icmp sle i32 %0, %1
%conv = zext i1 %cmp to i32
store i32 %conv, i32* @r1, align 4
-; 16: slt ${{[0-9]+}}, ${{[0-9]+}}
-; 16: move $[[REGISTER:[0-9]+]], $24
-; 16: xor $[[REGISTER]], ${{[0-9]+}}
+; 16: slt ${{[0-9]+}}, ${{[0-9]+}}
+; MMR6: slt ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}}
+; 16: move $[[REGISTER:[0-9]+]], $24
+; 16: xor $[[REGISTER]], ${{[0-9]+}}
%2 = load i32, i32* @m, align 4
%cmp1 = icmp sle i32 %2, %1
%conv2 = zext i1 %cmp1 to i32
diff --git a/llvm/test/CodeGen/Mips/setlt.ll b/llvm/test/CodeGen/Mips/setlt.ll
index 040f8b1..77ca71e 100644
--- a/llvm/test/CodeGen/Mips/setlt.ll
+++ b/llvm/test/CodeGen/Mips/setlt.ll
@@ -1,4 +1,5 @@
; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6
@j = global i32 -5, align 4
@k = global i32 10, align 4
@@ -15,7 +16,8 @@
%cmp = icmp slt i32 %0, %1
%conv = zext i1 %cmp to i32
store i32 %conv, i32* @r1, align 4
-; 16: slt ${{[0-9]+}}, ${{[0-9]+}}
-; 16: move ${{[0-9]+}}, $24
+; 16: slt ${{[0-9]+}}, ${{[0-9]+}}
+; MMR6: slt ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}}
+; 16: move ${{[0-9]+}}, $24
ret void
}
diff --git a/llvm/test/CodeGen/Mips/setltk.ll b/llvm/test/CodeGen/Mips/setltk.ll
index 79d25b1..aefe48b 100644
--- a/llvm/test/CodeGen/Mips/setltk.ll
+++ b/llvm/test/CodeGen/Mips/setltk.ll
@@ -1,4 +1,5 @@
; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc -march=mips -mattr=micromips -mcpu=mips32r6 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6
@j = global i32 -5, align 4
@k = global i32 10, align 4
@@ -14,7 +15,8 @@
%cmp = icmp slt i32 %0, 10
%conv = zext i1 %cmp to i32
store i32 %conv, i32* @r1, align 4
-; 16: slti $[[REGISTER:[0-9]+]], 10
-; 16: move $[[REGISTER]], $24
+; 16: slti $[[REGISTER:[0-9]+]], 10
+; MMR6: slti $[[REGISTER:[0-9]+]], $[[REGISTER:[0-9]+]], 10
+; 16: move $[[REGISTER]], $24
ret void
}
diff --git a/llvm/test/CodeGen/Mips/setne.ll b/llvm/test/CodeGen/Mips/setne.ll
index 02692bf..c2c0f1a 100644
--- a/llvm/test/CodeGen/Mips/setne.ll
+++ b/llvm/test/CodeGen/Mips/setne.ll
@@ -1,4 +1,5 @@
; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6
@i = global i32 1, align 4
@j = global i32 10, align 4
@@ -13,8 +14,9 @@
%cmp = icmp ne i32 %0, %1
%conv = zext i1 %cmp to i32
store i32 %conv, i32* @r1, align 4
-; 16: xor $[[REGISTER:[0-9]+]], ${{[0-9]+}}
-; 16: sltu ${{[0-9]+}}, $[[REGISTER]]
-; 16: move ${{[0-9]+}}, $24
+; 16: xor $[[REGISTER:[0-9]+]], ${{[0-9]+}}
+; 16: sltu ${{[0-9]+}}, $[[REGISTER]]
+; MMR6: sltu ${{[0-9]+}}, $zero, ${{[0-9]+}}
+; 16: move ${{[0-9]+}}, $24
ret void
}
diff --git a/llvm/test/CodeGen/Mips/setuge.ll b/llvm/test/CodeGen/Mips/setuge.ll
index 6ae77b6..dd9e5b5 100644
--- a/llvm/test/CodeGen/Mips/setuge.ll
+++ b/llvm/test/CodeGen/Mips/setuge.ll
@@ -1,4 +1,5 @@
; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6
@j = global i32 5, align 4
@k = global i32 10, align 4
@@ -15,9 +16,10 @@
%cmp = icmp uge i32 %0, %1
%conv = zext i1 %cmp to i32
store i32 %conv, i32* @r1, align 4
-; 16: sltu ${{[0-9]+}}, ${{[0-9]+}}
-; 16: move $[[REGISTER:[0-9]+]], $24
-; 16: xor $[[REGISTER]], ${{[0-9]+}}
+; 16: sltu ${{[0-9]+}}, ${{[0-9]+}}
+; MMR6: sltu ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}}
+; 16: move $[[REGISTER:[0-9]+]], $24
+; 16: xor $[[REGISTER]], ${{[0-9]+}}
%2 = load i32, i32* @m, align 4
%cmp1 = icmp uge i32 %0, %2
%conv2 = zext i1 %cmp1 to i32
diff --git a/llvm/test/CodeGen/Mips/setugt.ll b/llvm/test/CodeGen/Mips/setugt.ll
index f8de59b..9585485 100644
--- a/llvm/test/CodeGen/Mips/setugt.ll
+++ b/llvm/test/CodeGen/Mips/setugt.ll
@@ -1,4 +1,5 @@
; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6
@j = global i32 5, align 4
@k = global i32 10, align 4
@@ -15,7 +16,8 @@
%cmp = icmp ugt i32 %0, %1
%conv = zext i1 %cmp to i32
store i32 %conv, i32* @r1, align 4
-; 16: sltu ${{[0-9]+}}, ${{[0-9]+}}
-; 16: move ${{[0-9]+}}, $24
+; 16: sltu ${{[0-9]+}}, ${{[0-9]+}}
+; MMR6: sltu ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}}
+; 16: move ${{[0-9]+}}, $24
ret void
}
diff --git a/llvm/test/CodeGen/Mips/setule.ll b/llvm/test/CodeGen/Mips/setule.ll
index 8874d4d..ef18c62 100644
--- a/llvm/test/CodeGen/Mips/setule.ll
+++ b/llvm/test/CodeGen/Mips/setule.ll
@@ -1,4 +1,5 @@
; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6
@j = global i32 5, align 4
@k = global i32 10, align 4
@@ -15,9 +16,10 @@
%cmp = icmp ule i32 %0, %1
%conv = zext i1 %cmp to i32
store i32 %conv, i32* @r1, align 4
-; 16: sltu ${{[0-9]+}}, ${{[0-9]+}}
-; 16: move $[[REGISTER:[0-9]+]], $24
-; 16: xor $[[REGISTER]], ${{[0-9]+}}
+; 16: sltu ${{[0-9]+}}, ${{[0-9]+}}
+; MMR6: sltu ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}}
+; 16: move $[[REGISTER:[0-9]+]], $24
+; 16: xor $[[REGISTER]], ${{[0-9]+}}
%2 = load i32, i32* @m, align 4
%cmp1 = icmp ule i32 %2, %1
%conv2 = zext i1 %cmp1 to i32
diff --git a/llvm/test/CodeGen/Mips/setult.ll b/llvm/test/CodeGen/Mips/setult.ll
index 29c7588..b03e267 100644
--- a/llvm/test/CodeGen/Mips/setult.ll
+++ b/llvm/test/CodeGen/Mips/setult.ll
@@ -1,4 +1,5 @@
; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6
@j = global i32 5, align 4
@k = global i32 10, align 4
@@ -15,7 +16,8 @@
%cmp = icmp ult i32 %0, %1
%conv = zext i1 %cmp to i32
store i32 %conv, i32* @r1, align 4
-; 16: sltu ${{[0-9]+}}, ${{[0-9]+}}
-; 16: move ${{[0-9]+}}, $24
+; 16: sltu ${{[0-9]+}}, ${{[0-9]+}}
+; MMR6: sltu ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}}
+; 16: move ${{[0-9]+}}, $24
ret void
}
diff --git a/llvm/test/CodeGen/Mips/setultk.ll b/llvm/test/CodeGen/Mips/setultk.ll
index c1ef0aa..a0b0bbf 100644
--- a/llvm/test/CodeGen/Mips/setultk.ll
+++ b/llvm/test/CodeGen/Mips/setultk.ll
@@ -1,4 +1,5 @@
; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6
@j = global i32 5, align 4
@k = global i32 10, align 4
@@ -14,7 +15,8 @@
%cmp = icmp ult i32 %0, 10
%conv = zext i1 %cmp to i32
store i32 %conv, i32* @r1, align 4
-; 16: sltiu ${{[0-9]+}}, 10 # 16 bit inst
-; 16: move ${{[0-9]+}}, $24
+; 16: sltiu ${{[0-9]+}}, 10 # 16 bit inst
+; MMR6: sltiu ${{[0-9]+}}, ${{[0-9]+}}, 1
+; 16: move ${{[0-9]+}}, $24
ret void
}
diff --git a/llvm/test/CodeGen/Mips/slt.ll b/llvm/test/CodeGen/Mips/slt.ll
new file mode 100644
index 0000000..a17f5ab
--- /dev/null
+++ b/llvm/test/CodeGen/Mips/slt.ll
@@ -0,0 +1,18 @@
+; RUN: llc -march=mips -mcpu=mips32r3 -mattr=micromips -relocation-model=pic < %s | FileCheck %s
+
+define i32 @slt(i32 signext %a) nounwind readnone {
+ %1 = icmp slt i32 %a, 7
+ ; CHECK-LABEL: slt:
+ ; CHECK: slt ${{[0-9]+}}, ${{[0-9]+}}, $4
+ %2 = select i1 %1, i32 3, i32 4
+ ret i32 %2
+}
+
+define i32 @sgt(i32 signext %a) {
+entry:
+ ; CHECK-LABEL: sgt:
+ %cmp = icmp sgt i32 %a, 32767
+ ; CHECK: slt ${{[0-9]+}}, ${{[0-9]+}}, $4
+ %cond = select i1 %cmp, i32 7, i32 5
+ ret i32 %cond
+}