commit 2e59a45f80e5323bcc5c5c811a1aae86584daef2
author Tom Stellard <thomas.stellard@amd.com> Fri Jun 13 01:32:00 2014 +0000
committer Tom Stellard <thomas.stellard@amd.com> Fri Jun 13 01:32:00 2014 +0000
tree 9f4e11fd3eb46b7abbddfb4b39b7bf54c595d26f
parent d881e9195a7f612b08bf8e8c7f7a0a6040b2fee2

R600: Move AMDGPUInstrInfo from AMDGPUTargetMachine into AMDGPUSubtarget

llvm-svn: 210869

llvm/lib/Target/R600/R600InstrInfo.cpp

diff --git a/llvm/lib/Target/R600/R600InstrInfo.cpp b/llvm/lib/Target/R600/R600InstrInfo.cpp
index fc3c2c5..972349a 100644
--- a/llvm/lib/Target/R600/R600InstrInfo.cpp
+++ b/llvm/lib/Target/R600/R600InstrInfo.cpp
@@ -28,10 +28,9 @@
 #define GET_INSTRINFO_CTOR_DTOR
 #include "AMDGPUGenDFAPacketizer.inc"
 
-R600InstrInfo::R600InstrInfo(AMDGPUTargetMachine &tm)
-  : AMDGPUInstrInfo(tm),
-    RI(tm),
-    ST(tm.getSubtarget<AMDGPUSubtarget>())
+R600InstrInfo::R600InstrInfo(const AMDGPUSubtarget &st)
+  : AMDGPUInstrInfo(st),
+    RI(st)
   { }
 
 const R600RegisterInfo &R600InstrInfo::getRegisterInfo() const {
@@ -1221,7 +1220,6 @@
     const {
   assert (MI->getOpcode() == AMDGPU::DOT_4 && "Not Implemented");
   unsigned Opcode;
-  const AMDGPUSubtarget &ST = TM.getSubtarget<AMDGPUSubtarget>();
   if (ST.getGeneration() <= AMDGPUSubtarget::R700)
     Opcode = AMDGPU::DOT4_r600;
   else