commit 2e82883620196a42d57737a06ed4bb5ed5502de2
author Krzysztof Parzyszek <kparzysz@codeaurora.org> Tue Jul 14 20:11:28 2015 +0000
committer Krzysztof Parzyszek <kparzysz@codeaurora.org> Tue Jul 14 20:11:28 2015 +0000
tree 1382c0cbdd7cc5ace92be9b23242feaaaf7d2e8c
parent 9e6dea1df8eeb432b9f988e437202d1cd4897cfa

Fix Windows build: replace __func__ with LLVM_FUNCTION_NAME

llvm-svn: 242192

llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp

diff --git a/llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp b/llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp
index 9e31c64..6a97cd4 100644
--- a/llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp
@@ -202,7 +202,8 @@
 
 
 void HexagonGenPredicate::processPredicateGPR(const Register &Reg) {
-  DEBUG(dbgs() << __func__ << ": " << PrintReg(Reg.R, TRI, Reg.S) << "\n");
+  DEBUG(dbgs() << LLVM_FUNCTION_NAME << ": "
+               << PrintReg(Reg.R, TRI, Reg.S) << "\n");
   typedef MachineRegisterInfo::use_iterator use_iterator;
   use_iterator I = MRI->use_begin(Reg.R), E = MRI->use_end();
   if (I == E) {
@@ -229,7 +230,7 @@
   if (F != G2P.end())
     return F->second;
 
-  DEBUG(dbgs() << __func__ << ": " << PrintRegister(Reg, *TRI));
+  DEBUG(dbgs() << LLVM_FUNCTION_NAME << ": " << PrintRegister(Reg, *TRI));
   MachineInstr *DefI = MRI->getVRegDef(Reg.R);
   assert(DefI);
   unsigned Opc = DefI->getOpcode();
@@ -345,7 +346,7 @@
 
 
 bool HexagonGenPredicate::convertToPredForm(MachineInstr *MI) {
-  DEBUG(dbgs() << __func__ << ": " << MI << " " << *MI);
+  DEBUG(dbgs() << LLVM_FUNCTION_NAME << ": " << MI << " " << *MI);
 
   unsigned Opc = MI->getOpcode();
   assert(isConvertibleToPredForm(MI));
@@ -431,7 +432,7 @@
 
 
 bool HexagonGenPredicate::eliminatePredCopies(MachineFunction &MF) {
-  DEBUG(dbgs() << __func__ << "\n");
+  DEBUG(dbgs() << LLVM_FUNCTION_NAME << "\n");
   const TargetRegisterClass *PredRC = &Hexagon::PredRegsRegClass;
   bool Changed = false;
   VectOfInst Erase;