AArch64LoadStoreOptimizer: Update kill flags when merging stores
Kill flags need to be updated correctly when moving stores up/down to
form store pair instructions.
Those invalid flags have been ignored before but as of r290014 they are
recognized when using -mllvm -verify-machineinstrs.
Also simplifies test/CodeGen/AArch64/ldst-opt-dbg-limit.mir, renames it
to ldst-opt.mir test and adds a new tests for this change.
Differential Revision: https://reviews.llvm.org/D28875
llvm-svn: 292625
diff --git a/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp b/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
index 337b9ce..d780644 100644
--- a/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
+++ b/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
@@ -687,9 +687,30 @@
MachineInstrBuilder MIB;
DebugLoc DL = I->getDebugLoc();
MachineBasicBlock *MBB = I->getParent();
+ MachineOperand RegOp0 = getLdStRegOp(*RtMI);
+ MachineOperand RegOp1 = getLdStRegOp(*Rt2MI);
+ // Kill flags may become invalid when moving stores for pairing.
+ if (RegOp0.isUse()) {
+ if (!MergeForward) {
+ // Clear kill flags on store if moving upwards. Example:
+ // STRWui %w0, ...
+ // USE %w1
+ // STRWui kill %w1 ; need to clear kill flag when moving STRWui upwards
+ RegOp0.setIsKill(false);
+ RegOp1.setIsKill(false);
+ } else {
+ // Clear kill flags of the first stores register. Example:
+ // STRWui %w1, ...
+ // USE kill %w1 ; need to clear kill flag when moving STRWui downwards
+ // STRW %w0
+ unsigned Reg = getLdStRegOp(*I).getReg();
+ for (MachineInstr &MI : make_range(std::next(I), Paired))
+ MI.clearRegisterKills(Reg, TRI);
+ }
+ }
MIB = BuildMI(*MBB, InsertionPoint, DL, TII->get(getMatchingPairOpcode(Opc)))
- .add(getLdStRegOp(*RtMI))
- .add(getLdStRegOp(*Rt2MI))
+ .add(RegOp0)
+ .add(RegOp1)
.add(BaseRegOp)
.addImm(OffsetImm)
.setMemRefs(I->mergeMemRefsWith(*Paired));