[SystemZ] Implement conditional returns
Return is now considered a predicable instruction, and is converted
to a newly-added CondReturn (which maps to BCR to %r14) instruction by
the if conversion pass.
Also, fused compare-and-branch transform knows about conditional
returns, emitting the proper fused instructions for them.
This transform triggers on a *lot* of tests, hence the huge diffstat.
The changes are mostly jX to br %r14 -> bXr %r14.
Author: koriakin
Differential Revision: http://reviews.llvm.org/D17339
llvm-svn: 265689
diff --git a/llvm/test/CodeGen/SystemZ/int-cmp-36.ll b/llvm/test/CodeGen/SystemZ/int-cmp-36.ll
index 113d2c1..b17fedd 100644
--- a/llvm/test/CodeGen/SystemZ/int-cmp-36.ll
+++ b/llvm/test/CodeGen/SystemZ/int-cmp-36.ll
@@ -10,7 +10,7 @@
define i32 @f1(i32 %src1) {
; CHECK-LABEL: f1:
; CHECK: chrl %r2, g
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
; CHECK: br %r14
entry:
%val = load i16 , i16 *@g
@@ -47,7 +47,7 @@
define i32 @f3(i32 %src1) {
; CHECK-LABEL: f3:
; CHECK: chrl %r2, g
-; CHECK-NEXT: je
+; CHECK-NEXT: ber %r14
; CHECK: br %r14
entry:
%val = load i16 , i16 *@g
@@ -66,7 +66,7 @@
define i32 @f4(i32 %src1) {
; CHECK-LABEL: f4:
; CHECK: chrl %r2, g
-; CHECK-NEXT: jlh
+; CHECK-NEXT: blhr %r14
; CHECK: br %r14
entry:
%val = load i16 , i16 *@g
@@ -86,7 +86,7 @@
; CHECK-LABEL: f5:
; CHECK: lgrl [[REG:%r[0-5]]], h@GOT
; CHECK: ch %r2, 0([[REG]])
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
; CHECK: br %r14
entry:
%val = load i16 , i16 *@h, align 1
@@ -105,7 +105,7 @@
define i32 @f6(i32 %src2) {
; CHECK-LABEL: f6:
; CHECK: chrl %r2, g
-; CHECK-NEXT: jh {{\.L.*}}
+; CHECK-NEXT: bhr %r14
; CHECK: br %r14
entry:
%val = load i16 , i16 *@g