commit 2eca9d5ddfa02298301e77bd578de0d69c8445f3
author Eric Christopher <echristo@apple.com> Sat Jul 02 04:06:41 2011 +0000
committer Eric Christopher <echristo@apple.com> Sat Jul 02 04:06:41 2011 +0000
tree fb48f0fa2d1084f404149e2ed264ced4c83c2e48
parent 25a404eb810ff9181af22f10cc2ffd0320e43aaf

Be less specific about register allocation ordering.

llvm-svn: 134308

llvm/test/CodeGen/X86/atomic-or.ll

diff --git a/llvm/test/CodeGen/X86/atomic-or.ll b/llvm/test/CodeGen/X86/atomic-or.ll
index 9db6f6f..164252d 100644
--- a/llvm/test/CodeGen/X86/atomic-or.ll
+++ b/llvm/test/CodeGen/X86/atomic-or.ll
@@ -11,7 +11,7 @@
 ; CHECK: t1:
 ; CHECK: movl    $2147483648, %eax
 ; CHECK: lock
-; CHECK-NEXT: orq %rax, (%rdi)
+; CHECK-NEXT: orq %r{{.*}}, (%r{{.*}})
   %0 = call i64 @llvm.atomic.load.or.i64.p0i64(i64* %tmp, i64 2147483648)
   call void @llvm.memory.barrier(i1 true, i1 true, i1 true, i1 true, i1 true)
   ret void
@@ -26,7 +26,7 @@
 ; CHECK: t2:
 ; CHECK-NOT: movl
 ; CHECK: lock
-; CHECK-NEXT: orq $2147483644, (%rdi)
+; CHECK-NEXT: orq $2147483644, (%r{{.*}})
   %0 = call i64 @llvm.atomic.load.or.i64.p0i64(i64* %tmp, i64 2147483644)
   call void @llvm.memory.barrier(i1 true, i1 true, i1 true, i1 true, i1 true)
   ret void