R600/SI: Add processor types for each SI variant
Reviewed-by: Christian König <christian.koenig@amd.com>
llvm-svn: 178928
diff --git a/llvm/lib/Target/R600/AMDILDeviceInfo.cpp b/llvm/lib/Target/R600/AMDILDeviceInfo.cpp
index 9605fbe..19792b7 100644
--- a/llvm/lib/Target/R600/AMDILDeviceInfo.cpp
+++ b/llvm/lib/Target/R600/AMDILDeviceInfo.cpp
@@ -79,7 +79,9 @@
" on 32bit pointers!");
#endif
return new AMDGPUNIDevice(ptr);
- } else if (deviceName == "SI") {
+ } else if (deviceName == "SI" ||
+ deviceName == "tahiti" || deviceName == "pitcairn" ||
+ deviceName == "verde" || deviceName == "oland") {
return new AMDGPUSIDevice(ptr);
} else {
#if DEBUG
diff --git a/llvm/lib/Target/R600/Processors.td b/llvm/lib/Target/R600/Processors.td
index 868810c..3034c79 100644
--- a/llvm/lib/Target/R600/Processors.td
+++ b/llvm/lib/Target/R600/Processors.td
@@ -26,5 +26,8 @@
def : Proc<"turks", R600_EG_Itin, [FeatureByteAddress, FeatureImages]>;
def : Proc<"caicos", R600_EG_Itin, [FeatureByteAddress, FeatureImages]>;
def : Proc<"cayman", R600_EG_Itin, [FeatureByteAddress, FeatureImages, FeatureFP64]>;
-def : Proc<"SI", SI_Itin, [Feature64BitPtr]>;
-
+def : Proc<"SI", SI_Itin, [Feature64BitPtr, FeatureFP64]>;
+def : Proc<"tahiti", SI_Itin, [Feature64BitPtr, FeatureFP64]>;
+def : Proc<"pitcairn", SI_Itin, [Feature64BitPtr, FeatureFP64]>;
+def : Proc<"verde", SI_Itin, [Feature64BitPtr, FeatureFP64]>;
+def : Proc<"oland", SI_Itin, [Feature64BitPtr, FeatureFP64]>;
diff --git a/llvm/test/CodeGen/R600/imm.ll b/llvm/test/CodeGen/R600/imm.ll
index b43f9172..02b7309 100644
--- a/llvm/test/CodeGen/R600/imm.ll
+++ b/llvm/test/CodeGen/R600/imm.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s
+; RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s
; XXX: Enable once SI supports buffer stores
; XFAIL: *
diff --git a/llvm/test/CodeGen/R600/llvm.SI.fs.interp.constant.ll b/llvm/test/CodeGen/R600/llvm.SI.fs.interp.constant.ll
index bf0cdaa..e45722c 100644
--- a/llvm/test/CodeGen/R600/llvm.SI.fs.interp.constant.ll
+++ b/llvm/test/CodeGen/R600/llvm.SI.fs.interp.constant.ll
@@ -1,4 +1,4 @@
-;RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s
+;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s
;CHECK: S_MOV_B32
;CHECK-NEXT: V_INTERP_MOV_F32
diff --git a/llvm/test/CodeGen/R600/llvm.SI.sample.ll b/llvm/test/CodeGen/R600/llvm.SI.sample.ll
index c724395..5bdb246 100644
--- a/llvm/test/CodeGen/R600/llvm.SI.sample.ll
+++ b/llvm/test/CodeGen/R600/llvm.SI.sample.ll
@@ -1,4 +1,4 @@
-;RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s
+;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s
;CHECK: IMAGE_SAMPLE
;CHECK: IMAGE_SAMPLE
diff --git a/llvm/test/CodeGen/R600/lshl.ll b/llvm/test/CodeGen/R600/lshl.ll
index 423adb9..fb698da 100644
--- a/llvm/test/CodeGen/R600/lshl.ll
+++ b/llvm/test/CodeGen/R600/lshl.ll
@@ -1,4 +1,4 @@
-;RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s
+;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s
;CHECK: V_LSHLREV_B32_e32 VGPR0, 1, VGPR0
diff --git a/llvm/test/CodeGen/R600/lshr.ll b/llvm/test/CodeGen/R600/lshr.ll
index 551eac1..e0ed3ac 100644
--- a/llvm/test/CodeGen/R600/lshr.ll
+++ b/llvm/test/CodeGen/R600/lshr.ll
@@ -1,4 +1,4 @@
-;RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s
+;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s
;CHECK: V_LSHRREV_B32_e32 VGPR0, 1, VGPR0
diff --git a/llvm/test/CodeGen/R600/mulhu.ll b/llvm/test/CodeGen/R600/mulhu.ll
index 28744e0..bc17a59 100644
--- a/llvm/test/CodeGen/R600/mulhu.ll
+++ b/llvm/test/CodeGen/R600/mulhu.ll
@@ -1,4 +1,4 @@
-;RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s
+;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s
;CHECK: V_MOV_B32_e32 VGPR1, -1431655765
;CHECK-NEXT: V_MUL_HI_U32 VGPR0, VGPR0, VGPR1, 0, 0, 0, 0, 0
diff --git a/llvm/test/CodeGen/R600/seto.ll b/llvm/test/CodeGen/R600/seto.ll
index 5ab4b87..4622203 100644
--- a/llvm/test/CodeGen/R600/seto.ll
+++ b/llvm/test/CodeGen/R600/seto.ll
@@ -1,4 +1,4 @@
-;RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s
+;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s
;CHECK: V_CMP_O_F32_e64 SGPR0_SGPR1, VGPR0, VGPR0, 0, 0, 0, 0
diff --git a/llvm/test/CodeGen/R600/setuo.ll b/llvm/test/CodeGen/R600/setuo.ll
index 3208355..0bf5801 100644
--- a/llvm/test/CodeGen/R600/setuo.ll
+++ b/llvm/test/CodeGen/R600/setuo.ll
@@ -1,4 +1,4 @@
-;RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s
+;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s
;CHECK: V_CMP_U_F32_e64 SGPR0_SGPR1, VGPR0, VGPR0, 0, 0, 0, 0