AMDGPU: Dimension-aware image intrinsics
Summary:
These new image intrinsics contain the texture type as part of
their name and have each component of the address/coordinate as
individual parameters.
This is a preparatory step for implementing the A16 feature, where
coordinates are passed as half-floats or -ints, but the Z compare
value and texel offsets are still full dwords, making it difficult
or impossible to distinguish between A16 on or off in the old-style
intrinsics.
Additionally, these intrinsics pass the 'texfailpolicy' and
'cachectrl' as i32 bit fields to reduce operand clutter and allow
for future extensibility.
v2:
- gather4 supports 2darray images
- fix a bug with 1D images on SI
Change-Id: I099f309e0a394082a5901ea196c3967afb867f04
Reviewers: arsenm, rampitec, b-sumner
Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, llvm-commits, t-tye
Differential Revision: https://reviews.llvm.org/D44939
llvm-svn: 329166
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 2a7549e..6f68f63 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -3677,9 +3677,23 @@
Chain = Res.getValue(1);
return adjustLoadValueType(Res, LoadVT, DL, DAG, Unpacked);
}
- default:
+ default: {
+ const AMDGPU::D16ImageDimIntrinsic *D16ImageDimIntr =
+ AMDGPU::lookupD16ImageDimIntrinsicByIntr(IID);
+ if (D16ImageDimIntr) {
+ SmallVector<SDValue, 20> Ops;
+ for (auto Value : Op.getNode()->op_values())
+ Ops.push_back(Value);
+ Ops[1] = DAG.getConstant(D16ImageDimIntr->D16HelperIntr, DL, MVT::i32);
+ Res = DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, DL, VTList, Ops,
+ M->getMemoryVT(), M->getMemOperand());
+ Chain = Res.getValue(1);
+ return adjustLoadValueType(Res, LoadVT, DL, DAG, Unpacked);
+ }
+
return SDValue();
}
+ }
}
void SITargetLowering::ReplaceNodeResults(SDNode *N,
@@ -5151,9 +5165,32 @@
M->getMemoryVT(), M->getMemOperand());
}
- default:
+ default: {
+ const AMDGPU::D16ImageDimIntrinsic *D16ImageDimIntr =
+ AMDGPU::lookupD16ImageDimIntrinsicByIntr(IntrinsicID);
+ if (D16ImageDimIntr) {
+ SDValue VData = Op.getOperand(2);
+ EVT StoreVT = VData.getValueType();
+ if ((StoreVT == MVT::v2f16 && !isTypeLegal(StoreVT)) ||
+ StoreVT == MVT::v4f16) {
+ VData = handleD16VData(VData, DAG);
+
+ SmallVector<SDValue, 12> Ops;
+ for (auto Value : Op.getNode()->op_values())
+ Ops.push_back(Value);
+ Ops[1] = DAG.getConstant(D16ImageDimIntr->D16HelperIntr, DL, MVT::i32);
+ Ops[2] = VData;
+
+ MemSDNode *M = cast<MemSDNode>(Op);
+ return DAG.getMemIntrinsicNode(ISD::INTRINSIC_VOID, DL, Op->getVTList(),
+ Ops, M->getMemoryVT(),
+ M->getMemOperand());
+ }
+ }
+
return Op;
}
+ }
}
SDValue SITargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {