commit 3048b0248a9852fd1c4372a92e6fa1ed02ae9832
author Akira Hatanaka <ahatanaka@mips.com> Wed Oct 30 02:29:43 2013 +0000
committer Akira Hatanaka <ahatanaka@mips.com> Wed Oct 30 02:29:43 2013 +0000
tree 66d18b670ffa876be19643bb8d084bd800392cfc
parent 7245f1d85def56b5c1783876ebad9f2cecb6b827

[mips] Compute stack alignment on the fly.

llvm-svn: 193673

llvm/lib/Target/Mips/Mips.td

diff --git a/llvm/lib/Target/Mips/Mips.td b/llvm/lib/Target/Mips/Mips.td
index 0581d84..b8e3f39 100644
--- a/llvm/lib/Target/Mips/Mips.td
+++ b/llvm/lib/Target/Mips/Mips.td
@@ -30,12 +30,10 @@
 // Mips Subtarget features                                                    //
 //===----------------------------------------------------------------------===//
 
-def StackAlign16 : SubtargetFeature<"stackalign16", "StackAlignment", "16",
-                                    "Set stack alignment to 16-bytes.">;
 def FeatureGP64Bit     : SubtargetFeature<"gp64", "IsGP64bit", "true",
                                 "General Purpose Registers are 64-bit wide.">;
 def FeatureFP64Bit     : SubtargetFeature<"fp64", "IsFP64bit", "true",
-                                "Support 64-bit FP registers.", [StackAlign16]>;
+                                "Support 64-bit FP registers.">;
 def FeatureSingleFloat : SubtargetFeature<"single-float", "IsSingleFloat",
                                 "true", "Only supports single precision float">;
 def FeatureO32         : SubtargetFeature<"o32", "MipsABI", "O32",

llvm/lib/Target/Mips/MipsSubtarget.cpp

diff --git a/llvm/lib/Target/Mips/MipsSubtarget.cpp b/llvm/lib/Target/Mips/MipsSubtarget.cpp
index 07957ef..0a81072 100644
--- a/llvm/lib/Target/Mips/MipsSubtarget.cpp
+++ b/llvm/lib/Target/Mips/MipsSubtarget.cpp
@@ -72,7 +72,7 @@
   InMips16Mode(false), InMips16HardFloat(Mips16HardFloat),
   InMicroMipsMode(false), HasDSP(false), HasDSPR2(false),
   AllowMixed16_32(Mixed16_32 | Mips_Os16), Os16(Mips_Os16), HasMSA(false),
-  StackAlignment(8), RM(_RM), OverrideMode(NoOverride), TM(_TM)
+  RM(_RM), OverrideMode(NoOverride), TM(_TM)
 {
   std::string CPUName = CPU;
   if (CPUName.empty())

llvm/lib/Target/Mips/MipsSubtarget.h

diff --git a/llvm/lib/Target/Mips/MipsSubtarget.h b/llvm/lib/Target/Mips/MipsSubtarget.h
index 378fc00..7c17553 100644
--- a/llvm/lib/Target/Mips/MipsSubtarget.h
+++ b/llvm/lib/Target/Mips/MipsSubtarget.h
@@ -116,8 +116,6 @@
   // HasMSA -- supports MSA ASE.
   bool HasMSA;
 
-  unsigned StackAlignment;
-
   InstrItineraryData InstrItins;
 
   // The instance to the register info section object
@@ -219,7 +217,7 @@
 //
 static bool useConstantIslands();
 
-  unsigned stackAlignment() const { return StackAlignment; }
+  unsigned stackAlignment() const { return isFP64bit() ? 16 : 8; }
 
   // Grab MipsRegInfo object
   const MipsReginfo &getMReginfo() const { return MRI; }