commit 305bf5b21dbdb2345ef86b5700285e42d992c954
author Krzysztof Parzyszek <kparzysz@quicinc.com> Mon Jan 13 16:07:30 2020 -0600
committer Krzysztof Parzyszek <kparzysz@quicinc.com> Tue Jan 21 11:35:10 2020 -0600
tree 353c6c74794003f6e2b33371a0bd6a298a0b4f70
parent 7b8dc8c57697e95fd0b1248e4494ecc0f929aba1

[Hexagon] Add support for Hexagon v67t microarchitecture (tiny core)

llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp

diff --git a/llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp b/llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp
index 5b61d10..5821e72 100644
--- a/llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp
@@ -2836,6 +2836,9 @@
   if (MI.isCopy())
     return false;
 
+  MachineFunction *MF = MI.getParent()->getParent();
+  auto &HST = MF->getSubtarget<HexagonSubtarget>();
+
   // Collect all virtual register-def operands.
   SmallVector<unsigned,2> DefRegs;
   for (const MachineOperand &MO : MI.operands()) {
@@ -2923,11 +2926,13 @@
             NewMI = BuildMI(B, At, DL, *NewD, NewR)
                       .addImm(Hi)
                       .addImm(Lo);
-          } else {
+          } else if (MF->getFunction().hasOptSize() || !HST.isTinyCore()) {
+            // Disable CONST64 for tiny core since it takes a LD resource.
             NewD = &HII.get(Hexagon::CONST64);
             NewMI = BuildMI(B, At, DL, *NewD, NewR)
                       .addImm(V);
-          }
+          } else
+            return false;
         }
       }
       (void)NewMI;