Convert register liveness tracking to work on a sub-register level instead of just register units.
Reviewed by Andy
llvm-svn: 197315
diff --git a/llvm/lib/CodeGen/CMakeLists.txt b/llvm/lib/CodeGen/CMakeLists.txt
index 10cc9ff..0beca0c 100644
--- a/llvm/lib/CodeGen/CMakeLists.txt
+++ b/llvm/lib/CodeGen/CMakeLists.txt
@@ -35,7 +35,7 @@
LiveRangeCalc.cpp
LiveRangeEdit.cpp
LiveRegMatrix.cpp
- LiveRegUnits.cpp
+ LivePhysRegs.cpp
LiveStackAnalysis.cpp
LiveVariables.cpp
LocalStackSlotAllocation.cpp
diff --git a/llvm/lib/CodeGen/ExecutionDepsFix.cpp b/llvm/lib/CodeGen/ExecutionDepsFix.cpp
index f2a61ef..b31b029 100644
--- a/llvm/lib/CodeGen/ExecutionDepsFix.cpp
+++ b/llvm/lib/CodeGen/ExecutionDepsFix.cpp
@@ -23,7 +23,7 @@
#define DEBUG_TYPE "execution-fix"
#include "llvm/CodeGen/Passes.h"
#include "llvm/ADT/PostOrderIterator.h"
-#include "llvm/CodeGen/LiveRegUnits.h"
+#include "llvm/CodeGen/LivePhysRegs.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/Support/Allocator.h"
@@ -141,7 +141,7 @@
std::vector<std::pair<MachineInstr*, unsigned> > UndefReads;
/// Storage for register unit liveness.
- LiveRegUnits LiveUnits;
+ LivePhysRegs LiveRegSet;
/// Current instruction number.
/// The first instruction in each basic block is 0.
@@ -352,7 +352,7 @@
// Set up UndefReads to track undefined register reads.
UndefReads.clear();
- LiveUnits.clear();
+ LiveRegSet.clear();
// Set up LiveRegs to represent registers entering MBB.
if (!LiveRegs)
@@ -547,21 +547,19 @@
return;
// Collect this block's live out register units.
- LiveUnits.init(TRI);
- for (MachineBasicBlock::const_succ_iterator SI = MBB->succ_begin(),
- SE = MBB->succ_end(); SI != SE; ++SI) {
- LiveUnits.addLiveIns(*SI, *TRI);
- }
+ LiveRegSet.init(TRI);
+ LiveRegSet.addLiveOuts(MBB);
+
MachineInstr *UndefMI = UndefReads.back().first;
unsigned OpIdx = UndefReads.back().second;
for (MachineBasicBlock::reverse_iterator I = MBB->rbegin(), E = MBB->rend();
I != E; ++I) {
// Update liveness, including the current instruction's defs.
- LiveUnits.stepBackward(*I, *TRI);
+ LiveRegSet.stepBackward(*I);
if (UndefMI == &*I) {
- if (!LiveUnits.contains(UndefMI->getOperand(OpIdx).getReg(), *TRI))
+ if (!LiveRegSet.contains(UndefMI->getOperand(OpIdx).getReg()))
TII->breakPartialRegDependency(UndefMI, OpIdx, TRI);
UndefReads.pop_back();
diff --git a/llvm/lib/CodeGen/IfConversion.cpp b/llvm/lib/CodeGen/IfConversion.cpp
index e2d0eb4..c6cef9b 100644
--- a/llvm/lib/CodeGen/IfConversion.cpp
+++ b/llvm/lib/CodeGen/IfConversion.cpp
@@ -23,7 +23,7 @@
#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/TargetSchedule.h"
-#include "llvm/CodeGen/LiveRegUnits.h"
+#include "llvm/CodeGen/LivePhysRegs.h"
#include "llvm/MC/MCInstrItineraries.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
@@ -162,8 +162,8 @@
const MachineBranchProbabilityInfo *MBPI;
MachineRegisterInfo *MRI;
- LiveRegUnits Redefs;
- LiveRegUnits DontKill;
+ LivePhysRegs Redefs;
+ LivePhysRegs DontKill;
bool PreRegAlloc;
bool MadeChange;
@@ -968,23 +968,22 @@
/// Behaves like LiveRegUnits::StepForward() but also adds implicit uses to all
/// values defined in MI which are not live/used by MI.
-static void UpdatePredRedefs(MachineInstr *MI, LiveRegUnits &Redefs,
- const TargetRegisterInfo *TRI) {
+static void UpdatePredRedefs(MachineInstr *MI, LivePhysRegs &Redefs) {
for (ConstMIBundleOperands Ops(MI); Ops.isValid(); ++Ops) {
if (!Ops->isReg() || !Ops->isKill())
continue;
unsigned Reg = Ops->getReg();
if (Reg == 0)
continue;
- Redefs.removeReg(Reg, *TRI);
+ Redefs.removeReg(Reg);
}
for (MIBundleOperands Ops(MI); Ops.isValid(); ++Ops) {
if (!Ops->isReg() || !Ops->isDef())
continue;
unsigned Reg = Ops->getReg();
- if (Reg == 0 || Redefs.contains(Reg, *TRI))
+ if (Reg == 0 || Redefs.contains(Reg))
continue;
- Redefs.addReg(Reg, *TRI);
+ Redefs.addReg(Reg);
MachineOperand &Op = *Ops;
MachineInstr *MI = Op.getParent();
@@ -996,12 +995,11 @@
/**
* Remove kill flags from operands with a registers in the @p DontKill set.
*/
-static void RemoveKills(MachineInstr &MI, const LiveRegUnits &DontKill,
- const MCRegisterInfo &MCRI) {
+static void RemoveKills(MachineInstr &MI, const LivePhysRegs &DontKill) {
for (MIBundleOperands O(&MI); O.isValid(); ++O) {
if (!O->isReg() || !O->isKill())
continue;
- if (DontKill.contains(O->getReg(), MCRI))
+ if (DontKill.contains(O->getReg()))
O->setIsKill(false);
}
}
@@ -1012,10 +1010,10 @@
*/
static void RemoveKills(MachineBasicBlock::iterator I,
MachineBasicBlock::iterator E,
- const LiveRegUnits &DontKill,
+ const LivePhysRegs &DontKill,
const MCRegisterInfo &MCRI) {
for ( ; I != E; ++I)
- RemoveKills(*I, DontKill, MCRI);
+ RemoveKills(*I, DontKill);
}
/// IfConvertSimple - If convert a simple (split, no rejoin) sub-CFG.
@@ -1049,13 +1047,13 @@
// Initialize liveins to the first BB. These are potentiall redefined by
// predicated instructions.
Redefs.init(TRI);
- Redefs.addLiveIns(CvtBBI->BB, *TRI);
- Redefs.addLiveIns(NextBBI->BB, *TRI);
+ Redefs.addLiveIns(CvtBBI->BB);
+ Redefs.addLiveIns(NextBBI->BB);
// Compute a set of registers which must not be killed by instructions in
// BB1: This is everything live-in to BB2.
DontKill.init(TRI);
- DontKill.addLiveIns(NextBBI->BB, *TRI);
+ DontKill.addLiveIns(NextBBI->BB);
if (CvtBBI->BB->pred_size() > 1) {
BBI.NonPredSize -= TII->RemoveBranch(*BBI.BB);
@@ -1154,8 +1152,8 @@
// Initialize liveins to the first BB. These are potentially redefined by
// predicated instructions.
Redefs.init(TRI);
- Redefs.addLiveIns(CvtBBI->BB, *TRI);
- Redefs.addLiveIns(NextBBI->BB, *TRI);
+ Redefs.addLiveIns(CvtBBI->BB);
+ Redefs.addLiveIns(NextBBI->BB);
DontKill.clear();
@@ -1284,7 +1282,7 @@
// Initialize liveins to the first BB. These are potentially redefined by
// predicated instructions.
Redefs.init(TRI);
- Redefs.addLiveIns(BBI1->BB, *TRI);
+ Redefs.addLiveIns(BBI1->BB);
// Remove the duplicated instructions at the beginnings of both paths.
MachineBasicBlock::iterator DI1 = BBI1->BB->begin();
@@ -1317,12 +1315,12 @@
DontKill.init(TRI);
for (MachineBasicBlock::reverse_iterator I = BBI2->BB->rbegin(),
E = MachineBasicBlock::reverse_iterator(DI2); I != E; ++I) {
- DontKill.stepBackward(*I, *TRI);
+ DontKill.stepBackward(*I);
}
for (MachineBasicBlock::const_iterator I = BBI1->BB->begin(), E = DI1; I != E;
++I) {
- Redefs.stepForward(*I, *TRI);
+ Redefs.stepForward(*I);
}
BBI.BB->splice(BBI.BB->end(), BBI1->BB, BBI1->BB->begin(), DI1);
BBI2->BB->erase(BBI2->BB->begin(), DI2);
@@ -1506,7 +1504,7 @@
// If the predicated instruction now redefines a register as the result of
// if-conversion, add an implicit kill.
- UpdatePredRedefs(I, Redefs, TRI);
+ UpdatePredRedefs(I, Redefs);
}
std::copy(Cond.begin(), Cond.end(), std::back_inserter(BBI.Predicate));
@@ -1552,11 +1550,11 @@
// If the predicated instruction now redefines a register as the result of
// if-conversion, add an implicit kill.
- UpdatePredRedefs(MI, Redefs, TRI);
+ UpdatePredRedefs(MI, Redefs);
// Some kill flags may not be correct anymore.
if (!DontKill.empty())
- RemoveKills(*MI, DontKill, *TRI);
+ RemoveKills(*MI, DontKill);
}
if (!IgnoreBr) {
diff --git a/llvm/lib/CodeGen/LivePhysRegs.cpp b/llvm/lib/CodeGen/LivePhysRegs.cpp
new file mode 100644
index 0000000..7efd941
--- /dev/null
+++ b/llvm/lib/CodeGen/LivePhysRegs.cpp
@@ -0,0 +1,114 @@
+//===--- LivePhysRegs.cpp - Live Physical Register Set --------------------===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements the LivePhysRegs utility for tracking liveness of
+// physical registers across machine instructions in forward or backward order.
+// A more detailed description can be found in the corresponding header file.
+//
+//===----------------------------------------------------------------------===//
+
+#include "llvm/CodeGen/LivePhysRegs.h"
+#include "llvm/CodeGen/MachineInstrBundle.h"
+#include "llvm/Support/Debug.h"
+using namespace llvm;
+
+
+/// \brief Remove all registers from the set that get clobbered by the register
+/// mask.
+void LivePhysRegs::removeRegsInMask(const MachineOperand &MO) {
+ SparseSet<unsigned>::iterator LRI = LiveRegs.begin();
+ while (LRI != LiveRegs.end()) {
+ if (MO.clobbersPhysReg(*LRI))
+ LRI = LiveRegs.erase(LRI);
+ else
+ ++LRI;
+ }
+}
+
+/// Simulates liveness when stepping backwards over an instruction(bundle):
+/// Remove Defs, add uses. This is the recommended way of calculating liveness.
+void LivePhysRegs::stepBackward(const MachineInstr &MI) {
+ // Remove defined registers and regmask kills from the set.
+ for (ConstMIBundleOperands O(&MI); O.isValid(); ++O) {
+ if (O->isReg()) {
+ if (!O->isDef())
+ continue;
+ unsigned Reg = O->getReg();
+ if (Reg == 0)
+ continue;
+ removeReg(Reg);
+ } else if (O->isRegMask())
+ removeRegsInMask(*O);
+ }
+
+ // Add uses to the set.
+ for (ConstMIBundleOperands O(&MI); O.isValid(); ++O) {
+ if (!O->isReg() || !O->readsReg() || O->isUndef())
+ continue;
+ unsigned Reg = O->getReg();
+ if (Reg == 0)
+ continue;
+ addReg(Reg);
+ }
+}
+
+/// Simulates liveness when stepping forward over an instruction(bundle): Remove
+/// killed-uses, add defs. This is the not recommended way, because it depends
+/// on accurate kill flags. If possible use stepBackwards() instead of this
+/// function.
+void LivePhysRegs::stepForward(const MachineInstr &MI) {
+ SmallVector<unsigned, 4> Defs;
+ // Remove killed registers from the set.
+ for (ConstMIBundleOperands O(&MI); O.isValid(); ++O) {
+ if (O->isReg()) {
+ unsigned Reg = O->getReg();
+ if (Reg == 0)
+ continue;
+ if (O->isDef()) {
+ if (!O->isDead())
+ Defs.push_back(Reg);
+ } else {
+ if (!O->isKill())
+ continue;
+ assert(O->isUse());
+ removeReg(Reg);
+ }
+ } else if (O->isRegMask())
+ removeRegsInMask(*O);
+ }
+
+ // Add defs to the set.
+ for (unsigned i = 0, e = Defs.size(); i != e; ++i)
+ addReg(Defs[i]);
+}
+
+/// Prin the currently live registers to OS.
+void LivePhysRegs::print(raw_ostream &OS) const {
+ OS << "Live Registers:";
+ if (!TRI) {
+ OS << " (uninitialized)\n";
+ return;
+ }
+
+ if (empty()) {
+ OS << " (empty)\n";
+ return;
+ }
+
+ for (const_iterator I = begin(), E = end(); I != E; ++I)
+ OS << " " << PrintReg(*I, TRI);
+ OS << "\n";
+}
+
+/// Dumps the currently live registers to the debug output.
+void LivePhysRegs::dump() const {
+#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
+ dbgs() << " " << *this;
+#endif
+}
diff --git a/llvm/lib/CodeGen/LiveRegUnits.cpp b/llvm/lib/CodeGen/LiveRegUnits.cpp
deleted file mode 100644
index 6221ca2..0000000
--- a/llvm/lib/CodeGen/LiveRegUnits.cpp
+++ /dev/null
@@ -1,111 +0,0 @@
-//===-- LiveInterval.cpp - Live Interval Representation -------------------===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file implements the LiveRegUnits utility for tracking liveness of
-// physical register units across machine instructions in forward or backward
-// order.
-//
-//===----------------------------------------------------------------------===//
-
-#include "llvm/CodeGen/LiveRegUnits.h"
-#include "llvm/CodeGen/MachineInstrBundle.h"
-using namespace llvm;
-
-/// Return true if the given MachineOperand clobbers the given register unit.
-/// A register unit is only clobbered if all its super-registers are clobbered.
-static bool operClobbersUnit(const MachineOperand *MO, unsigned Unit,
- const MCRegisterInfo *MCRI) {
- for (MCRegUnitRootIterator RI(Unit, MCRI); RI.isValid(); ++RI) {
- for (MCSuperRegIterator SI(*RI, MCRI, true); SI.isValid(); ++SI) {
- if (!MO->clobbersPhysReg(*SI))
- return false;
- }
- }
- return true;
-}
-
-/// We assume the high bits of a physical super register are not preserved
-/// unless the instruction has an implicit-use operand reading the
-/// super-register or a register unit for the upper bits is available.
-void LiveRegUnits::removeRegsInMask(const MachineOperand &Op,
- const MCRegisterInfo &MCRI) {
- SparseSet<unsigned>::iterator LUI = LiveUnits.begin();
- while (LUI != LiveUnits.end()) {
- if (operClobbersUnit(&Op, *LUI, &MCRI))
- LUI = LiveUnits.erase(LUI);
- else
- ++LUI;
- }
-}
-
-void LiveRegUnits::stepBackward(const MachineInstr &MI,
- const MCRegisterInfo &MCRI) {
- // Remove defined registers and regmask kills from the set.
- for (ConstMIBundleOperands O(&MI); O.isValid(); ++O) {
- if (O->isReg()) {
- if (!O->isDef())
- continue;
- unsigned Reg = O->getReg();
- if (Reg == 0)
- continue;
- removeReg(Reg, MCRI);
- } else if (O->isRegMask()) {
- removeRegsInMask(*O, MCRI);
- }
- }
- // Add uses to the set.
- for (ConstMIBundleOperands O(&MI); O.isValid(); ++O) {
- if (!O->isReg() || !O->readsReg() || O->isUndef())
- continue;
- unsigned Reg = O->getReg();
- if (Reg == 0)
- continue;
- addReg(Reg, MCRI);
- }
-}
-
-/// Uses with kill flag get removed from the set, defs added. If possible
-/// use StepBackward() instead of this function because some kill flags may
-/// be missing.
-void LiveRegUnits::stepForward(const MachineInstr &MI,
- const MCRegisterInfo &MCRI) {
- SmallVector<unsigned, 4> Defs;
- // Remove killed registers from the set.
- for (ConstMIBundleOperands O(&MI); O.isValid(); ++O) {
- if (O->isReg()) {
- unsigned Reg = O->getReg();
- if (Reg == 0)
- continue;
- if (O->isDef()) {
- if (!O->isDead())
- Defs.push_back(Reg);
- } else {
- if (!O->isKill())
- continue;
- assert(O->isUse());
- removeReg(Reg, MCRI);
- }
- } else if (O->isRegMask()) {
- removeRegsInMask(*O, MCRI);
- }
- }
- // Add defs to the set.
- for (unsigned i = 0, e = Defs.size(); i != e; ++i) {
- addReg(Defs[i], MCRI);
- }
-}
-
-/// Adds all registers in the live-in list of block @p BB.
-void LiveRegUnits::addLiveIns(const MachineBasicBlock *MBB,
- const MCRegisterInfo &MCRI) {
- for (MachineBasicBlock::livein_iterator L = MBB->livein_begin(),
- LE = MBB->livein_end(); L != LE; ++L) {
- addReg(*L, MCRI);
- }
-}