commit 31c039ef2e16a85cd5ac15defabfaf9ddcd50f60
author Matt Arsenault <Matthew.Arsenault@amd.com> Thu Jan 12 18:48:09 2017 +0000
committer Matt Arsenault <Matthew.Arsenault@amd.com> Thu Jan 12 18:48:09 2017 +0000
tree 8400fa174f41b53b7b689e018a74c63fc9bb54ff
parent 555e5980a5c7037fba5b40e8bab556a17e272511

AMDGPU: Fold free fneg into sin

llvm-svn: 291790

llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp

diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
index a6c5e06..7771b23 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
@@ -2813,8 +2813,10 @@
   case ISD::FMUL:
   case ISD::FMA:
   case ISD::FMAD:
+  case ISD::FSIN:
   case AMDGPUISD::RCP:
   case AMDGPUISD::RCP_LEGACY:
+  case AMDGPUISD::SIN_HW:
   case AMDGPUISD::FMUL_LEGACY:
     return true;
   default:
@@ -2906,7 +2908,9 @@
   }
   case ISD::FP_EXTEND:
   case AMDGPUISD::RCP:
-  case AMDGPUISD::RCP_LEGACY: {
+  case AMDGPUISD::RCP_LEGACY:
+  case ISD::FSIN:
+  case AMDGPUISD::SIN_HW: {
     SDValue CvtSrc = N0.getOperand(0);
     if (CvtSrc.getOpcode() == ISD::FNEG) {
       // (fneg (fp_extend (fneg x))) -> (fp_extend x)