commit 321cf3c65091c64f50d55ffb50817882cd908865
author Igor Breger <igor.breger@intel.com> Fri Mar 03 08:06:46 2017 +0000
committer Igor Breger <igor.breger@intel.com> Fri Mar 03 08:06:46 2017 +0000
tree 379feec4d56b2793537c4c4d67b2c6c2a3e486e8
parent 6007b5f71370a43caf950068ab07db9abb78a840

[GlobalISel][X86] Support float/double and vector types.

Summary: [GlobalISel][X86] Add support for f32/f64 and vector types in RegisterBank and InstructionSelector.

Reviewers: delena, zvi

Reviewed By: zvi

Subscribers: dberris, rovka, llvm-commits, kristof.beyls

Differential Revision: https://reviews.llvm.org/D30533

llvm-svn: 296856

llvm/lib/Target/X86/X86LegalizerInfo.cpp

diff --git a/llvm/lib/Target/X86/X86LegalizerInfo.cpp b/llvm/lib/Target/X86/X86LegalizerInfo.cpp
index 5f63f8d..06c11c8 100644
--- a/llvm/lib/Target/X86/X86LegalizerInfo.cpp
+++ b/llvm/lib/Target/X86/X86LegalizerInfo.cpp
@@ -19,6 +19,7 @@
 #include "llvm/Target/TargetOpcodes.h"
 
 using namespace llvm;
+using namespace TargetOpcode;
 
 #ifndef LLVM_BUILD_GLOBAL_ISEL
 #error "You shouldn't build this"
@@ -28,6 +29,8 @@
 
   setLegalizerInfo32bit();
   setLegalizerInfo64bit();
+  setLegalizerInfoSSE1();
+  setLegalizerInfoSSE2();
 
   computeTables();
 }
@@ -39,8 +42,8 @@
   const LLT s32 = LLT::scalar(32);
 
   for (auto Ty : {s8, s16, s32}) {
-    setAction({TargetOpcode::G_ADD, Ty}, Legal);
-    setAction({TargetOpcode::G_SUB, Ty}, Legal);
+    setAction({G_ADD, Ty}, Legal);
+    setAction({G_SUB, Ty}, Legal);
   }
 }
 
@@ -51,6 +54,36 @@
 
   const LLT s64 = LLT::scalar(64);
 
-  setAction({TargetOpcode::G_ADD, s64}, Legal);
-  setAction({TargetOpcode::G_SUB, s64}, Legal);
+  setAction({G_ADD, s64}, Legal);
+  setAction({G_SUB, s64}, Legal);
+}
+
+void X86LegalizerInfo::setLegalizerInfoSSE1() {
+  if (!Subtarget.hasSSE1())
+    return;
+
+  const LLT s32 = LLT::scalar(32);
+  const LLT v4s32 = LLT::vector(4, 32);
+
+  for (unsigned BinOp : {G_FADD, G_FSUB, G_FMUL, G_FDIV})
+    for (auto Ty : {s32, v4s32})
+      setAction({BinOp, Ty}, Legal);
+}
+
+void X86LegalizerInfo::setLegalizerInfoSSE2() {
+  if (!Subtarget.hasSSE2())
+    return;
+
+  const LLT s64 = LLT::scalar(64);
+  const LLT v4s32 = LLT::vector(4, 32);
+  const LLT v2s64 = LLT::vector(2, 64);
+
+  for (unsigned BinOp : {G_FADD, G_FSUB, G_FMUL, G_FDIV})
+    for (auto Ty : {s64, v2s64})
+      setAction({BinOp, Ty}, Legal);
+
+  for (unsigned BinOp : {G_ADD, G_SUB})
+    for (auto Ty : {v4s32})
+      setAction({BinOp, Ty}, Legal);
+
 }