| commit | 32c6b5cb70b5aedf6df2835570052545e5c888b7 | [log] [tgz] |
|---|---|---|
| author | Dmitry Preobrazhensky <dmitry.preobrazhensky@amd.com> | Wed Jun 13 17:02:03 2018 +0000 |
| committer | Dmitry Preobrazhensky <dmitry.preobrazhensky@amd.com> | Wed Jun 13 17:02:03 2018 +0000 |
| tree | 0c53229e943b923e512bd57c63faaeb871d2bcf9 | |
| parent | 54a138a0c50e0050e5ea4d419315e8ef41aaff4a [diff] [blame] |
[AMDGPU][MC] Enabled parsing of relocations on VALU instructions See bug 37566: https://bugs.llvm.org/show_bug.cgi?id=37566 Reviewers: artem.tamazov, arsenm, nhaehnle Differential Revision: https://reviews.llvm.org/D47884 llvm-svn: 334622
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp index 1888cec..18cc67f 100644 --- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp +++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -443,7 +443,7 @@ } bool isVSrcB32() const { - return isVCSrcF32() || isLiteralImm(MVT::i32); + return isVCSrcF32() || isLiteralImm(MVT::i32) || isExpr(); } bool isVSrcB64() const { @@ -460,7 +460,7 @@ } bool isVSrcF32() const { - return isVCSrcF32() || isLiteralImm(MVT::f32); + return isVCSrcF32() || isLiteralImm(MVT::f32) || isExpr(); } bool isVSrcF64() const {