[llvm-exegesis][NFC] internal changes
Summary:
BitVectors are now cached to lower memory utilization.
Instructions have reference semantics.
Reviewers: courbet
Subscribers: sdardis, tschuett, jrtc27, atanasyan, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D71653
diff --git a/llvm/unittests/tools/llvm-exegesis/X86/SnippetGeneratorTest.cpp b/llvm/unittests/tools/llvm-exegesis/X86/SnippetGeneratorTest.cpp
index 463eec2..0f898d9 100644
--- a/llvm/unittests/tools/llvm-exegesis/X86/SnippetGeneratorTest.cpp
+++ b/llvm/unittests/tools/llvm-exegesis/X86/SnippetGeneratorTest.cpp
@@ -86,8 +86,8 @@
ASSERT_THAT(CT.Instructions, SizeIs(1));
const InstructionTemplate &IT = CT.Instructions[0];
EXPECT_THAT(IT.getOpcode(), Opcode);
- ASSERT_THAT(IT.VariableValues, SizeIs(1)); // Imm.
- EXPECT_THAT(IT.VariableValues[0], IsInvalid()) << "Immediate is not set";
+ ASSERT_THAT(IT.getVariableValues(), SizeIs(1)); // Imm.
+ EXPECT_THAT(IT.getVariableValues()[0], IsInvalid()) << "Immediate is not set";
}
TEST_F(LatencySnippetGeneratorTest, ImplicitSelfDependencyThroughTiedRegs) {
@@ -109,9 +109,9 @@
ASSERT_THAT(CT.Instructions, SizeIs(1));
const InstructionTemplate &IT = CT.Instructions[0];
EXPECT_THAT(IT.getOpcode(), Opcode);
- ASSERT_THAT(IT.VariableValues, SizeIs(2));
- EXPECT_THAT(IT.VariableValues[0], IsInvalid()) << "Operand 1 is not set";
- EXPECT_THAT(IT.VariableValues[1], IsInvalid()) << "Operand 2 is not set";
+ ASSERT_THAT(IT.getVariableValues(), SizeIs(2));
+ EXPECT_THAT(IT.getVariableValues()[0], IsInvalid()) << "Operand 1 is not set";
+ EXPECT_THAT(IT.getVariableValues()[1], IsInvalid()) << "Operand 2 is not set";
}
TEST_F(LatencySnippetGeneratorTest, ImplicitSelfDependencyThroughExplicitRegs) {
@@ -131,8 +131,8 @@
ASSERT_THAT(CT.Instructions, SizeIs(1));
const InstructionTemplate &IT = CT.Instructions[0];
EXPECT_THAT(IT.getOpcode(), Opcode);
- ASSERT_THAT(IT.VariableValues, SizeIs(3));
- EXPECT_THAT(IT.VariableValues,
+ ASSERT_THAT(IT.getVariableValues(), SizeIs(3));
+ EXPECT_THAT(IT.getVariableValues(),
AnyOf(ElementsAre(IsReg(), IsInvalid(), IsReg()),
ElementsAre(IsReg(), IsReg(), IsInvalid())))
<< "Op0 is either set to Op1 or to Op2";
@@ -173,9 +173,10 @@
ASSERT_THAT(CT.Instructions, SizeIs(2));
const InstructionTemplate &IT = CT.Instructions[0];
EXPECT_THAT(IT.getOpcode(), Opcode);
- ASSERT_THAT(IT.VariableValues, SizeIs(2));
- EXPECT_THAT(IT.VariableValues, AnyOf(ElementsAre(IsReg(), IsInvalid()),
- ElementsAre(IsInvalid(), IsReg())));
+ ASSERT_THAT(IT.getVariableValues(), SizeIs(2));
+ EXPECT_THAT(IT.getVariableValues(),
+ AnyOf(ElementsAre(IsReg(), IsInvalid()),
+ ElementsAre(IsInvalid(), IsReg())));
EXPECT_THAT(CT.Instructions[1].getOpcode(), Not(Opcode));
// TODO: check that the two instructions alias each other.
}
@@ -193,7 +194,7 @@
ASSERT_THAT(CT.Instructions, SizeIs(2));
const InstructionTemplate &IT = CT.Instructions[0];
EXPECT_THAT(IT.getOpcode(), Opcode);
- ASSERT_THAT(IT.VariableValues, SizeIs(0));
+ ASSERT_THAT(IT.getVariableValues(), SizeIs(0));
}
}
@@ -212,9 +213,9 @@
ASSERT_THAT(CT.Instructions, SizeIs(1));
const InstructionTemplate &IT = CT.Instructions[0];
EXPECT_THAT(IT.getOpcode(), Opcode);
- ASSERT_THAT(IT.VariableValues, SizeIs(2));
- EXPECT_THAT(IT.VariableValues[0], IsInvalid());
- EXPECT_THAT(IT.VariableValues[1], IsInvalid());
+ ASSERT_THAT(IT.getVariableValues(), SizeIs(2));
+ EXPECT_THAT(IT.getVariableValues()[0], IsInvalid());
+ EXPECT_THAT(IT.getVariableValues()[1], IsInvalid());
}
TEST_F(UopsSnippetGeneratorTest, SerialInstruction) {
@@ -233,7 +234,7 @@
ASSERT_THAT(CT.Instructions, SizeIs(1));
const InstructionTemplate &IT = CT.Instructions[0];
EXPECT_THAT(IT.getOpcode(), Opcode);
- ASSERT_THAT(IT.VariableValues, SizeIs(0));
+ ASSERT_THAT(IT.getVariableValues(), SizeIs(0));
}
TEST_F(UopsSnippetGeneratorTest, StaticRenaming) {
@@ -260,8 +261,8 @@
ASSERT_THAT(CT.Instructions, SizeIs(kInstructionCount));
std::unordered_set<unsigned> AllDefRegisters;
for (const auto &IT : CT.Instructions) {
- ASSERT_THAT(IT.VariableValues, SizeIs(3));
- AllDefRegisters.insert(IT.VariableValues[0].getReg());
+ ASSERT_THAT(IT.getVariableValues(), SizeIs(3));
+ AllDefRegisters.insert(IT.getVariableValues()[0].getReg());
}
EXPECT_THAT(AllDefRegisters, SizeIs(kInstructionCount))
<< "Each instruction writes to a different register";
@@ -291,12 +292,14 @@
ASSERT_THAT(CT.Instructions, SizeIs(1));
const InstructionTemplate &IT = CT.Instructions[0];
EXPECT_THAT(IT.getOpcode(), Opcode);
- ASSERT_THAT(IT.VariableValues, SizeIs(4));
- EXPECT_THAT(IT.VariableValues[0].getReg(), Not(IT.VariableValues[1].getReg()))
+ ASSERT_THAT(IT.getVariableValues(), SizeIs(4));
+ EXPECT_THAT(IT.getVariableValues()[0].getReg(),
+ Not(IT.getVariableValues()[1].getReg()))
<< "Def is different from first Use";
- EXPECT_THAT(IT.VariableValues[0].getReg(), Not(IT.VariableValues[2].getReg()))
+ EXPECT_THAT(IT.getVariableValues()[0].getReg(),
+ Not(IT.getVariableValues()[2].getReg()))
<< "Def is different from second Use";
- EXPECT_THAT(IT.VariableValues[3], IsInvalid());
+ EXPECT_THAT(IT.getVariableValues()[3], IsInvalid());
}
TEST_F(UopsSnippetGeneratorTest, MemoryUse) {
@@ -326,11 +329,11 @@
SizeIs(UopsSnippetGenerator::kMinNumDifferentAddresses));
const InstructionTemplate &IT = CT.Instructions[0];
EXPECT_THAT(IT.getOpcode(), Opcode);
- ASSERT_THAT(IT.VariableValues, SizeIs(6));
- EXPECT_EQ(IT.VariableValues[2].getImm(), 1);
- EXPECT_EQ(IT.VariableValues[3].getReg(), 0u);
- EXPECT_EQ(IT.VariableValues[4].getImm(), 0);
- EXPECT_EQ(IT.VariableValues[5].getReg(), 0u);
+ ASSERT_THAT(IT.getVariableValues(), SizeIs(6));
+ EXPECT_EQ(IT.getVariableValues()[2].getImm(), 1);
+ EXPECT_EQ(IT.getVariableValues()[3].getReg(), 0u);
+ EXPECT_EQ(IT.getVariableValues()[4].getImm(), 0);
+ EXPECT_EQ(IT.getVariableValues()[5].getReg(), 0u);
}
class FakeSnippetGenerator : public SnippetGenerator {
@@ -338,10 +341,14 @@
FakeSnippetGenerator(const LLVMState &State, const Options &Opts)
: SnippetGenerator(State, Opts) {}
- Instruction createInstruction(unsigned Opcode) {
+ const Instruction &getInstr(unsigned Opcode) {
return State.getIC().getInstr(Opcode);
}
+ InstructionTemplate getInstructionTemplate(unsigned Opcode) {
+ return {&getInstr(Opcode)};
+ }
+
private:
Expected<std::vector<CodeTemplate>>
generateCodeTemplates(const Instruction &, const BitVector &) const override {
@@ -389,8 +396,8 @@
// explicit use 1 : reg RegClass=GR16 | TIED_TO:0
// explicit use 2 : imm
// implicit def : EFLAGS
- InstructionTemplate IT(Generator.createInstruction(X86::ADD16ri));
- IT.getValueFor(IT.Instr.Variables[0]) = MCOperand::createReg(X86::AX);
+ InstructionTemplate IT = Generator.getInstructionTemplate(X86::ADD16ri);
+ IT.getValueFor(IT.getInstr().Variables[0]) = MCOperand::createReg(X86::AX);
std::vector<InstructionTemplate> Snippet;
Snippet.push_back(std::move(IT));
const auto RIV = Generator.computeRegisterInitialValues(Snippet);
@@ -404,15 +411,18 @@
// -> only rbx needs defining.
std::vector<InstructionTemplate> Snippet;
{
- InstructionTemplate Mov(Generator.createInstruction(X86::MOV64ri));
- Mov.getValueFor(Mov.Instr.Variables[0]) = MCOperand::createReg(X86::RAX);
- Mov.getValueFor(Mov.Instr.Variables[1]) = MCOperand::createImm(42);
+ InstructionTemplate Mov = Generator.getInstructionTemplate(X86::MOV64ri);
+ Mov.getValueFor(Mov.getInstr().Variables[0]) =
+ MCOperand::createReg(X86::RAX);
+ Mov.getValueFor(Mov.getInstr().Variables[1]) = MCOperand::createImm(42);
Snippet.push_back(std::move(Mov));
}
{
- InstructionTemplate Add(Generator.createInstruction(X86::ADD64rr));
- Add.getValueFor(Add.Instr.Variables[0]) = MCOperand::createReg(X86::RAX);
- Add.getValueFor(Add.Instr.Variables[1]) = MCOperand::createReg(X86::RBX);
+ InstructionTemplate Add = Generator.getInstructionTemplate(X86::ADD64rr);
+ Add.getValueFor(Add.getInstr().Variables[0]) =
+ MCOperand::createReg(X86::RAX);
+ Add.getValueFor(Add.getInstr().Variables[1]) =
+ MCOperand::createReg(X86::RBX);
Snippet.push_back(std::move(Add));
}