[llvm-exegesis][NFC] internal changes
Summary:
BitVectors are now cached to lower memory utilization.
Instructions have reference semantics.
Reviewers: courbet
Subscribers: sdardis, tschuett, jrtc27, atanasyan, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D71653
diff --git a/llvm/unittests/tools/llvm-exegesis/X86/TargetTest.cpp b/llvm/unittests/tools/llvm-exegesis/X86/TargetTest.cpp
index e15b7f2..eefed6d 100644
--- a/llvm/unittests/tools/llvm-exegesis/X86/TargetTest.cpp
+++ b/llvm/unittests/tools/llvm-exegesis/X86/TargetTest.cpp
@@ -119,6 +119,10 @@
Value);
}
+ const Instruction &getInstr(unsigned OpCode) {
+ return State.getIC().getInstr(OpCode);
+ }
+
LLVMState State;
};
@@ -355,8 +359,8 @@
}
TEST_F(Core2Avx512TargetTest, FillMemoryOperands_ADD64rm) {
- Instruction I(State.getInstrInfo(), State.getRATC(), X86::ADD64rm);
- InstructionTemplate IT(I);
+ const Instruction &I = getInstr(X86::ADD64rm);
+ InstructionTemplate IT(&I);
constexpr const int kOffset = 42;
State.getExegesisTarget().fillMemoryOperands(IT, X86::RDI, kOffset);
// Memory is operands 2-6.
@@ -368,8 +372,8 @@
}
TEST_F(Core2Avx512TargetTest, FillMemoryOperands_VGATHERDPSZ128rm) {
- Instruction I(State.getInstrInfo(), State.getRATC(), X86::VGATHERDPSZ128rm);
- InstructionTemplate IT(I);
+ const Instruction &I = getInstr(X86::VGATHERDPSZ128rm);
+ InstructionTemplate IT(&I);
constexpr const int kOffset = 42;
State.getExegesisTarget().fillMemoryOperands(IT, X86::RDI, kOffset);
// Memory is operands 4-8.