| commit | 32d4d37e614f005e981f61ad278808f6da213bca | [log] [tgz] |
|---|---|---|
| author | Chad Rosier <mcrosier@codeaurora.org> | Tue Sep 29 16:07:32 2015 +0000 |
| committer | Chad Rosier <mcrosier@codeaurora.org> | Tue Sep 29 16:07:32 2015 +0000 |
| tree | 61c8d7c22c3109eb707bbfcf2d0e9dc78a0c7c35 | |
| parent | dc0541f12f6dfa2c4a91d2f12bd86ed6f0f65bd5 [diff] |
[AArch64] Scale offsets by the size of the memory operation. NFC. The immediate in the load/store should be scaled by the size of the memory operation, not the size of the register being loaded/stored. This change gets us one step closer to forming LDPSW instructions. This change also enables pre- and post-indexing for halfword and byte loads and stores. llvm-svn: 248804