Change -mno-mmx to be more compatible with gcc. Specifically, -mno-mmx should not imply -mno-sse.
Note that because we don't usually touch the MMX registers anyway, all -mno-mmx needs to do is tweak the x86-32 calling convention a little for vectors that look like MMX vectors, and prevent the definition of __MMX__.
clang doesn't actually stop the user from using MMX inline asm operands or MMX builtins in -mno-mmx mode; as a QOI issue, it would be nice to diagnose, but I doubt it really matters much.
<rdar://problem/9694837>
llvm-svn: 134770
diff --git a/clang/test/CodeGen/x86_32-arguments-darwin.c b/clang/test/CodeGen/x86_32-arguments-darwin.c
index f7e2a53..83f0f64 100644
--- a/clang/test/CodeGen/x86_32-arguments-darwin.c
+++ b/clang/test/CodeGen/x86_32-arguments-darwin.c
@@ -1,5 +1,4 @@
-// RUN: %clang_cc1 -w -fblocks -triple i386-apple-darwin9 -emit-llvm -o %t %s
-// RUN: FileCheck < %t %s
+// RUN: %clang_cc1 -w -fblocks -triple i386-apple-darwin9 -target-cpu yonah -emit-llvm -o - %s | FileCheck %s
// CHECK: define signext i8 @f0()
char f0(void) {
diff --git a/clang/test/CodeGen/x86_32-arguments-linux.c b/clang/test/CodeGen/x86_32-arguments-linux.c
index 2f246f8..81dcaf6 100644
--- a/clang/test/CodeGen/x86_32-arguments-linux.c
+++ b/clang/test/CodeGen/x86_32-arguments-linux.c
@@ -1,4 +1,4 @@
-// RUN: %clang_cc1 -w -fblocks -triple i386-pc-linux-gnu -emit-llvm -o %t %s
+// RUN: %clang_cc1 -w -fblocks -triple i386-pc-linux-gnu -target-cpu pentium4 -emit-llvm -o %t %s
// RUN: FileCheck < %t %s
// CHECK: define void @f56(
diff --git a/clang/test/CodeGen/x86_32-arguments-nommx.c b/clang/test/CodeGen/x86_32-arguments-nommx.c
new file mode 100644
index 0000000..d503ed0
--- /dev/null
+++ b/clang/test/CodeGen/x86_32-arguments-nommx.c
@@ -0,0 +1,11 @@
+// RUN: %clang_cc1 -target-feature -mmx -target-feature +sse2 -triple i686-pc-linux-gnu -emit-llvm -o - %s | FileCheck %s
+
+// no-mmx should put mmx into memory
+typedef int __attribute__((vector_size (8))) i32v2;
+int a(i32v2 x) { return x[0]; }
+// CHECK: define i32 @a(i64 %x.coerce)
+
+// but SSE2 vectors should still go into an SSE2 register
+typedef int __attribute__((vector_size (16))) i32v4;
+int b(i32v4 x) { return x[0]; }
+// CHECK: define i32 @b(<4 x i32> %x.coerce)