commit 33a1a0b0014e0ca3e189a7252e70ab5b11a3e608
author Tim Northover <tnorthover@apple.com> Tue Jan 17 23:04:01 2017 +0000
committer Tim Northover <tnorthover@apple.com> Tue Jan 17 23:04:01 2017 +0000
tree b352efcdbd9edddfcb3eb1465397eed62df28a6b
parent 509091f9e0f5a3526263a0875cb773a3f535d908

GlobalISel: fix comparison order for G_FCMP

As with G_ICMP we'd written the CSET instructions backwards.

llvm-svn: 292285

llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp

diff --git a/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
index b514735..f856537 100644
--- a/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
+++ b/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
@@ -1134,7 +1134,7 @@
              .addDef(Def1Reg)
              .addUse(AArch64::WZR)
              .addUse(AArch64::WZR)
-             .addImm(CC1);
+             .addImm(getInvertedCondCode(CC1));
 
     if (CC2 != AArch64CC::AL) {
       unsigned Def2Reg = MRI.createVirtualRegister(&AArch64::GPR32RegClass);
@@ -1143,7 +1143,7 @@
                .addDef(Def2Reg)
                .addUse(AArch64::WZR)
                .addUse(AArch64::WZR)
-               .addImm(CC2);
+               .addImm(getInvertedCondCode(CC2));
       MachineInstr &OrMI =
           *BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::ORRWrr))
                .addDef(DefReg)