commit 33e694a8077809dc414145d65a31f73068c85589
author Dan Gohman <dan433584@gmail.com> Thu May 12 04:19:09 2016 +0000
committer Dan Gohman <dan433584@gmail.com> Thu May 12 04:19:09 2016 +0000
tree 04d59b2c5d3e682996e18b9221170c9348f23400
parent 1fb10e846a22f0569372f71c1ad2d68997d70779

[WebAssembly] Fast-isel support for calls, arguments, and selects.

llvm-svn: 269273

llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp

diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp
index 8a00d54..1e6d5f0 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp
@@ -297,13 +297,14 @@
   unsigned NewReg = MRI.createVirtualRegister(RegClass);
   unsigned TeeReg = MRI.createVirtualRegister(RegClass);
   unsigned DefReg = MRI.createVirtualRegister(RegClass);
+  MachineOperand &DefMO = Def->getOperand(0);
   MRI.replaceRegWith(Reg, NewReg);
   MachineInstr *Tee = BuildMI(MBB, Insert, Insert->getDebugLoc(),
                               TII->get(GetTeeLocalOpcode(RegClass)), TeeReg)
                           .addReg(NewReg, RegState::Define)
-                          .addReg(DefReg);
+                          .addReg(DefReg, getUndefRegState(DefMO.isDead()));
   Op.setReg(TeeReg);
-  Def->getOperand(0).setReg(DefReg);
+  DefMO.setReg(DefReg);
   LIS.InsertMachineInstrInMaps(*Tee);
   LIS.removeInterval(Reg);
   LIS.createAndComputeVirtRegInterval(NewReg);