GlobalISel: support same ConstantExprs as Instructions.
It's more than just inttoptr, but the others can't be tested until we have
support for non-trivial constants (they currently get unavoidably folded to a
ConstantInt).
llvm-svn: 278303
diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
index 788823d..0f06b54 100644
--- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
@@ -84,25 +84,25 @@
return *MBB;
}
-bool IRTranslator::translateBinaryOp(unsigned Opcode,
- const BinaryOperator &Inst) {
+bool IRTranslator::translateBinaryOp(unsigned Opcode, const User &U) {
// FIXME: handle signed/unsigned wrapping flags.
// Get or create a virtual register for each value.
// Unless the value is a Constant => loadimm cst?
// or inline constant each time?
// Creation of a virtual register needs to have a size.
- unsigned Op0 = getOrCreateVReg(*Inst.getOperand(0));
- unsigned Op1 = getOrCreateVReg(*Inst.getOperand(1));
- unsigned Res = getOrCreateVReg(Inst);
- MIRBuilder.buildInstr(Opcode, LLT{*Inst.getType()})
+ unsigned Op0 = getOrCreateVReg(*U.getOperand(0));
+ unsigned Op1 = getOrCreateVReg(*U.getOperand(1));
+ unsigned Res = getOrCreateVReg(U);
+ MIRBuilder.buildInstr(Opcode, LLT{*U.getType()})
.addDef(Res)
.addUse(Op0)
.addUse(Op1);
return true;
}
-bool IRTranslator::translateReturn(const ReturnInst &RI) {
+bool IRTranslator::translateRet(const User &U) {
+ const ReturnInst &RI = cast<ReturnInst>(U);
const Value *Ret = RI.getReturnValue();
// The target may mess up with the insertion point, but
// this is not important as a return is the last instruction
@@ -110,7 +110,8 @@
return CLI->lowerReturn(MIRBuilder, Ret, !Ret ? 0 : getOrCreateVReg(*Ret));
}
-bool IRTranslator::translateBr(const BranchInst &BrInst) {
+bool IRTranslator::translateBr(const User &U) {
+ const BranchInst &BrInst = cast<BranchInst>(U);
unsigned Succ = 0;
if (!BrInst.isUnconditional()) {
// We want a G_BRCOND to the true BB followed by an unconditional branch.
@@ -131,7 +132,8 @@
return true;
}
-bool IRTranslator::translateLoad(const LoadInst &LI) {
+bool IRTranslator::translateLoad(const User &U) {
+ const LoadInst &LI = cast<LoadInst>(U);
assert(LI.isSimple() && "only simple loads are supported at the moment");
MachineFunction &MF = MIRBuilder.getMF();
@@ -147,7 +149,8 @@
return true;
}
-bool IRTranslator::translateStore(const StoreInst &SI) {
+bool IRTranslator::translateStore(const User &U) {
+ const StoreInst &SI = cast<StoreInst>(U);
assert(SI.isSimple() && "only simple loads are supported at the moment");
MachineFunction &MF = MIRBuilder.getMF();
@@ -164,28 +167,30 @@
return true;
}
-bool IRTranslator::translateBitCast(const CastInst &CI) {
- if (LLT{*CI.getDestTy()} == LLT{*CI.getSrcTy()}) {
- unsigned &Reg = ValToVReg[&CI];
+bool IRTranslator::translateBitCast(const User &U) {
+ if (LLT{*U.getOperand(0)->getType()} == LLT{*U.getType()}) {
+ unsigned &Reg = ValToVReg[&U];
if (Reg)
- MIRBuilder.buildCopy(Reg, getOrCreateVReg(*CI.getOperand(0)));
+ MIRBuilder.buildCopy(Reg, getOrCreateVReg(*U.getOperand(0)));
else
- Reg = getOrCreateVReg(*CI.getOperand(0));
+ Reg = getOrCreateVReg(*U.getOperand(0));
return true;
}
- return translateCast(TargetOpcode::G_BITCAST, CI);
+ return translateCast(TargetOpcode::G_BITCAST, U);
}
-bool IRTranslator::translateCast(unsigned Opcode, const CastInst &CI) {
- unsigned Op = getOrCreateVReg(*CI.getOperand(0));
- unsigned Res = getOrCreateVReg(CI);
- MIRBuilder.buildInstr(Opcode, {LLT{*CI.getDestTy()}, LLT{*CI.getSrcTy()}})
+bool IRTranslator::translateCast(unsigned Opcode, const User &U) {
+ unsigned Op = getOrCreateVReg(*U.getOperand(0));
+ unsigned Res = getOrCreateVReg(U);
+ MIRBuilder
+ .buildInstr(Opcode, {LLT{*U.getType()}, LLT{*U.getOperand(0)->getType()}})
.addDef(Res)
.addUse(Op);
return true;
}
-bool IRTranslator::translateCall(const CallInst &CI) {
+bool IRTranslator::translateCall(const User &U) {
+ const CallInst &CI = cast<CallInst>(U);
auto TII = MIRBuilder.getMF().getTarget().getIntrinsicInfo();
const Function *F = CI.getCalledFunction();
@@ -246,7 +251,8 @@
return true;
}
-bool IRTranslator::translatePhi(const PHINode &PI) {
+bool IRTranslator::translatePHI(const User &U) {
+ const PHINode &PI = cast<PHINode>(U);
MachineInstrBuilder MIB = MIRBuilder.buildInstr(TargetOpcode::PHI);
MIB.addDef(getOrCreateVReg(PI));
@@ -277,59 +283,11 @@
bool IRTranslator::translate(const Instruction &Inst) {
MIRBuilder.setDebugLoc(Inst.getDebugLoc());
switch(Inst.getOpcode()) {
- // Arithmetic operations.
- case Instruction::Add:
- return translateBinaryOp(TargetOpcode::G_ADD, cast<BinaryOperator>(Inst));
- case Instruction::Sub:
- return translateBinaryOp(TargetOpcode::G_SUB, cast<BinaryOperator>(Inst));
-
- // Bitwise operations.
- case Instruction::And:
- return translateBinaryOp(TargetOpcode::G_AND, cast<BinaryOperator>(Inst));
- case Instruction::Mul:
- return translateBinaryOp(TargetOpcode::G_MUL, cast<BinaryOperator>(Inst));
- case Instruction::Or:
- return translateBinaryOp(TargetOpcode::G_OR, cast<BinaryOperator>(Inst));
- case Instruction::Xor:
- return translateBinaryOp(TargetOpcode::G_XOR, cast<BinaryOperator>(Inst));
-
- // Branch operations.
- case Instruction::Br:
- return translateBr(cast<BranchInst>(Inst));
- case Instruction::Ret:
- return translateReturn(cast<ReturnInst>(Inst));
-
- // Calls
- case Instruction::Call:
- return translateCall(cast<CallInst>(Inst));
-
- // Casts and allied operations
- case Instruction::BitCast:
- return translateBitCast(cast<CastInst>(Inst));
- case Instruction::IntToPtr:
- return translateCast(TargetOpcode::G_INTTOPTR, cast<CastInst>(Inst));
- case Instruction::PtrToInt:
- return translateCast(TargetOpcode::G_PTRTOINT, cast<CastInst>(Inst));
- case Instruction::Trunc:
- return translateCast(TargetOpcode::G_TRUNC, cast<CastInst>(Inst));
-
- // Memory ops.
- case Instruction::Load:
- return translateLoad(cast<LoadInst>(Inst));
- case Instruction::Store:
- return translateStore(cast<StoreInst>(Inst));
-
- case Instruction::Alloca:
- return translateStaticAlloca(cast<AllocaInst>(Inst));
-
- case Instruction::PHI:
- return translatePhi(cast<PHINode>(Inst));
-
- case Instruction::Unreachable:
- return true;
-
+#define HANDLE_INST(NUM, OPCODE, CLASS) \
+ case Instruction::OPCODE: return translate##OPCODE(Inst);
+#include "llvm/IR/Instruction.def"
default:
- llvm_unreachable("Opcode not supported");
+ llvm_unreachable("unknown opcode");
}
}
@@ -338,7 +296,15 @@
EntryBuilder.buildConstant(LLT{*CI->getType()}, Reg, CI->getZExtValue());
else if (isa<UndefValue>(C))
EntryBuilder.buildInstr(TargetOpcode::IMPLICIT_DEF).addDef(Reg);
- else
+ else if (auto CE = dyn_cast<ConstantExpr>(&C)) {
+ switch(CE->getOpcode()) {
+#define HANDLE_INST(NUM, OPCODE, CLASS) \
+ case Instruction::OPCODE: return translate##OPCODE(*CE);
+#include "llvm/IR/Instruction.def"
+ default:
+ llvm_unreachable("unknown opcode");
+ }
+ } else
llvm_unreachable("unhandled constant kind");
return true;