AMDGPU/GlobalISel: Select flat loads
Now that the patterns use the new PatFrag address space support, the
only blocker to importing most load patterns is the addressing mode
complex patterns.
llvm-svn: 366237
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
index 14ae629..39016ed 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
@@ -2937,18 +2937,11 @@
SDValue N1 = Addr.getOperand(1);
int64_t COffsetVal = cast<ConstantSDNode>(N1)->getSExtValue();
- if (ST.getGeneration() >= AMDGPUSubtarget::GFX10) {
- if ((IsSigned && isInt<12>(COffsetVal)) ||
- (!IsSigned && isUInt<11>(COffsetVal))) {
- Addr = N0;
- OffsetVal = COffsetVal;
- }
- } else {
- if ((IsSigned && isInt<13>(COffsetVal)) ||
- (!IsSigned && isUInt<12>(COffsetVal))) {
- Addr = N0;
- OffsetVal = COffsetVal;
- }
+ const SIInstrInfo *TII = ST.getInstrInfo();
+ if (TII->isLegalFLATOffset(COffsetVal, findMemSDNode(N)->getAddressSpace(),
+ IsSigned)) {
+ Addr = N0;
+ OffsetVal = COffsetVal;
}
}