Change TargetParser enum names to avoid macro conflicts (llvm)
sys/time.h on Solaris (and possibly other systems) defines "SEC" as "1"
using a cpp macro. The result is that this fails to compile.
Fixes https://llvm.org/PR23482
llvm-svn: 237112
diff --git a/llvm/lib/Support/TargetParser.cpp b/llvm/lib/Support/TargetParser.cpp
index d4dcbc8..78d0c57 100644
--- a/llvm/lib/Support/TargetParser.cpp
+++ b/llvm/lib/Support/TargetParser.cpp
@@ -27,20 +27,20 @@
const char * Name;
ARM::FPUKind ID;
} FPUNames[] = {
- { "invalid", ARM::INVALID_FPU },
- { "vfp", ARM::VFP },
- { "vfpv2", ARM::VFPV2 },
- { "vfpv3", ARM::VFPV3 },
- { "vfpv3-d16", ARM::VFPV3_D16 },
- { "vfpv4", ARM::VFPV4 },
- { "vfpv4-d16", ARM::VFPV4_D16 },
- { "fpv5-d16", ARM::FPV5_D16 },
- { "fp-armv8", ARM::FP_ARMV8 },
- { "neon", ARM::NEON },
- { "neon-vfpv4", ARM::NEON_VFPV4 },
- { "neon-fp-armv8", ARM::NEON_FP_ARMV8 },
- { "crypto-neon-fp-armv8", ARM::CRYPTO_NEON_FP_ARMV8 },
- { "softvfp", ARM::SOFTVFP }
+ { "invalid", ARM::FK_INVALID },
+ { "vfp", ARM::FK_VFP },
+ { "vfpv2", ARM::FK_VFPV2 },
+ { "vfpv3", ARM::FK_VFPV3 },
+ { "vfpv3-d16", ARM::FK_VFPV3_D16 },
+ { "vfpv4", ARM::FK_VFPV4 },
+ { "vfpv4-d16", ARM::FK_VFPV4_D16 },
+ { "fpv5-d16", ARM::FK_FPV5_D16 },
+ { "fp-armv8", ARM::FK_FP_ARMV8 },
+ { "neon", ARM::FK_NEON },
+ { "neon-vfpv4", ARM::FK_NEON_VFPV4 },
+ { "neon-fp-armv8", ARM::FK_NEON_FP_ARMV8 },
+ { "crypto-neon-fp-armv8", ARM::FK_CRYPTO_NEON_FP_ARMV8 },
+ { "softvfp", ARM::FK_SOFTVFP }
};
// List of canonical arch names (use getArchSynonym)
// FIXME: TableGen this.
@@ -50,31 +50,31 @@
const char *DefaultCPU;
ARMBuildAttrs::CPUArch DefaultArch;
} ARCHNames[] = {
- { "invalid", ARM::INVALID_ARCH, nullptr, ARMBuildAttrs::CPUArch::Pre_v4 },
- { "armv2", ARM::ARMV2, "2", ARMBuildAttrs::CPUArch::v4 },
- { "armv2a", ARM::ARMV2A, "2A", ARMBuildAttrs::CPUArch::v4 },
- { "armv3", ARM::ARMV3, "3", ARMBuildAttrs::CPUArch::v4 },
- { "armv3m", ARM::ARMV3M, "3M", ARMBuildAttrs::CPUArch::v4 },
- { "armv4", ARM::ARMV4, "4", ARMBuildAttrs::CPUArch::v4 },
- { "armv4t", ARM::ARMV4T, "4T", ARMBuildAttrs::CPUArch::v4T },
- { "armv5", ARM::ARMV5, "5", ARMBuildAttrs::CPUArch::v5T },
- { "armv5t", ARM::ARMV5T, "5T", ARMBuildAttrs::CPUArch::v5T },
- { "armv5te", ARM::ARMV5TE, "5TE", ARMBuildAttrs::CPUArch::v5TE },
- { "armv6", ARM::ARMV6, "6", ARMBuildAttrs::CPUArch::v6 },
- { "armv6j", ARM::ARMV6J, "6J", ARMBuildAttrs::CPUArch::v6 },
- { "armv6k", ARM::ARMV6K, "6K", ARMBuildAttrs::CPUArch::v6K },
- { "armv6t2", ARM::ARMV6T2, "6T2", ARMBuildAttrs::CPUArch::v6T2 },
- { "armv6z", ARM::ARMV6Z, "6Z", ARMBuildAttrs::CPUArch::v6KZ },
- { "armv6zk", ARM::ARMV6ZK, "6ZK", ARMBuildAttrs::CPUArch::v6KZ },
- { "armv6-m", ARM::ARMV6M, "6-M", ARMBuildAttrs::CPUArch::v6_M },
- { "armv7", ARM::ARMV7, "7", ARMBuildAttrs::CPUArch::v7 },
- { "armv7-a", ARM::ARMV7A, "7-A", ARMBuildAttrs::CPUArch::v7 },
- { "armv7-r", ARM::ARMV7R, "7-R", ARMBuildAttrs::CPUArch::v7 },
- { "armv7-m", ARM::ARMV7M, "7-M", ARMBuildAttrs::CPUArch::v7 },
- { "armv8-a", ARM::ARMV8A, "8-A", ARMBuildAttrs::CPUArch::v8 },
- { "armv8.1-a", ARM::ARMV8_1A, "8.1-A", ARMBuildAttrs::CPUArch::v8 },
- { "iwmmxt", ARM::IWMMXT, "iwmmxt", ARMBuildAttrs::CPUArch::v5TE },
- { "iwmmxt2", ARM::IWMMXT2, "iwmmxt2", ARMBuildAttrs::CPUArch::v5TE }
+ { "invalid", ARM::AK_INVALID, nullptr, ARMBuildAttrs::CPUArch::Pre_v4 },
+ { "armv2", ARM::AK_ARMV2, "2", ARMBuildAttrs::CPUArch::v4 },
+ { "armv2a", ARM::AK_ARMV2A, "2A", ARMBuildAttrs::CPUArch::v4 },
+ { "armv3", ARM::AK_ARMV3, "3", ARMBuildAttrs::CPUArch::v4 },
+ { "armv3m", ARM::AK_ARMV3M, "3M", ARMBuildAttrs::CPUArch::v4 },
+ { "armv4", ARM::AK_ARMV4, "4", ARMBuildAttrs::CPUArch::v4 },
+ { "armv4t", ARM::AK_ARMV4T, "4T", ARMBuildAttrs::CPUArch::v4T },
+ { "armv5", ARM::AK_ARMV5, "5", ARMBuildAttrs::CPUArch::v5T },
+ { "armv5t", ARM::AK_ARMV5T, "5T", ARMBuildAttrs::CPUArch::v5T },
+ { "armv5te", ARM::AK_ARMV5TE, "5TE", ARMBuildAttrs::CPUArch::v5TE },
+ { "armv6", ARM::AK_ARMV6, "6", ARMBuildAttrs::CPUArch::v6 },
+ { "armv6j", ARM::AK_ARMV6J, "6J", ARMBuildAttrs::CPUArch::v6 },
+ { "armv6k", ARM::AK_ARMV6K, "6K", ARMBuildAttrs::CPUArch::v6K },
+ { "armv6t2", ARM::AK_ARMV6T2, "6T2", ARMBuildAttrs::CPUArch::v6T2 },
+ { "armv6z", ARM::AK_ARMV6Z, "6Z", ARMBuildAttrs::CPUArch::v6KZ },
+ { "armv6zk", ARM::AK_ARMV6ZK, "6ZK", ARMBuildAttrs::CPUArch::v6KZ },
+ { "armv6-m", ARM::AK_ARMV6M, "6-M", ARMBuildAttrs::CPUArch::v6_M },
+ { "armv7", ARM::AK_ARMV7, "7", ARMBuildAttrs::CPUArch::v7 },
+ { "armv7-a", ARM::AK_ARMV7A, "7-A", ARMBuildAttrs::CPUArch::v7 },
+ { "armv7-r", ARM::AK_ARMV7R, "7-R", ARMBuildAttrs::CPUArch::v7 },
+ { "armv7-m", ARM::AK_ARMV7M, "7-M", ARMBuildAttrs::CPUArch::v7 },
+ { "armv8-a", ARM::AK_ARMV8A, "8-A", ARMBuildAttrs::CPUArch::v8 },
+ { "armv8.1-a", ARM::AK_ARMV8_1A, "8.1-A", ARMBuildAttrs::CPUArch::v8 },
+ { "iwmmxt", ARM::AK_IWMMXT, "iwmmxt", ARMBuildAttrs::CPUArch::v5TE },
+ { "iwmmxt2", ARM::AK_IWMMXT2, "iwmmxt2", ARMBuildAttrs::CPUArch::v5TE }
};
// List of canonical ARCH names (use getARCHSynonym)
// FIXME: TableGen this.
@@ -82,14 +82,14 @@
const char *Name;
ARM::ArchExtKind ID;
} ARCHExtNames[] = {
- { "invalid", ARM::INVALID_ARCHEXT },
- { "crc", ARM::CRC },
- { "crypto", ARM::CRYPTO },
- { "fp", ARM::FP },
- { "idiv", ARM::HWDIV },
- { "mp", ARM::MP },
- { "sec", ARM::SEC },
- { "virt", ARM::VIRT }
+ { "invalid", ARM::AEK_INVALID },
+ { "crc", ARM::AEK_CRC },
+ { "crypto", ARM::AEK_CRYPTO },
+ { "fp", ARM::AEK_FP },
+ { "idiv", ARM::AEK_HWDIV },
+ { "mp", ARM::AEK_MP },
+ { "sec", ARM::AEK_SEC },
+ { "virt", ARM::AEK_VIRT }
};
} // namespace
@@ -101,31 +101,31 @@
// ======================================================= //
const char *ARMTargetParser::getFPUName(unsigned ID) {
- if (ID >= ARM::LAST_FPU)
+ if (ID >= ARM::FK_LAST)
return nullptr;
return FPUNames[ID].Name;
}
const char *ARMTargetParser::getArchName(unsigned ID) {
- if (ID >= ARM::LAST_ARCH)
+ if (ID >= ARM::AK_LAST)
return nullptr;
return ARCHNames[ID].Name;
}
const char *ARMTargetParser::getArchDefaultCPUName(unsigned ID) {
- if (ID >= ARM::LAST_ARCH)
+ if (ID >= ARM::AK_LAST)
return nullptr;
return ARCHNames[ID].DefaultCPU;
}
unsigned ARMTargetParser::getArchDefaultCPUArch(unsigned ID) {
- if (ID >= ARM::LAST_ARCH)
+ if (ID >= ARM::AK_LAST)
return 0;
return ARCHNames[ID].DefaultArch;
}
const char *ARMTargetParser::getArchExtName(unsigned ID) {
- if (ID >= ARM::LAST_ARCHEXT)
+ if (ID >= ARM::AEK_LAST)
return nullptr;
return ARCHExtNames[ID].Name;
}
@@ -170,7 +170,7 @@
if (Syn == F.Name)
return F.ID;
}
- return ARM::INVALID_FPU;
+ return ARM::FK_INVALID;
}
unsigned ARMTargetParser::parseArch(StringRef Arch) {
@@ -179,7 +179,7 @@
if (Syn == A.Name)
return A.ID;
}
- return ARM::INVALID_ARCH;
+ return ARM::AK_INVALID;
}
unsigned ARMTargetParser::parseArchExt(StringRef ArchExt) {
@@ -187,7 +187,7 @@
if (ArchExt == A.Name)
return A.ID;
}
- return ARM::INVALID_ARCHEXT;
+ return ARM::AEK_INVALID;
}
} // namespace llvm