[AMDGPU] Divergence driven instruction selection. Part 1.
Summary: This change is the first part of the AMDGPU target description
change. The aim of it is the effective splitting the vector and scalar
flows at the selection stage. Selection uses predicate functions based
on the framework implemented earlier - https://reviews.llvm.org/D35267
Differential revision: https://reviews.llvm.org/D52019
Reviewers: rampitec
llvm-svn: 342719
diff --git a/llvm/test/CodeGen/AMDGPU/add.ll b/llvm/test/CodeGen/AMDGPU/add.ll
index 1fdc14f..6a108db8 100644
--- a/llvm/test/CodeGen/AMDGPU/add.ll
+++ b/llvm/test/CodeGen/AMDGPU/add.ll
@@ -121,7 +121,7 @@
; FUNC-LABEL: {{^}}v_add_i32:
; GCN: {{buffer|flat|global}}_load_dword [[A:v[0-9]+]]
; GCN: {{buffer|flat|global}}_load_dword [[B:v[0-9]+]]
-; SIVI: v_add_{{i|u}}32_e32 v{{[0-9]+}}, vcc, [[B]], [[A]]
+; SIVI: v_add_{{i|u}}32_e32 v{{[0-9]+}}, vcc, [[A]], [[B]]
; GFX9: v_add_u32_e32 v{{[0-9]+}}, [[A]], [[B]]
define amdgpu_kernel void @v_add_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 {
%tid = call i32 @llvm.r600.read.tidig.x()
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.private-memory.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.private-memory.ll
index 048bb30..f93c96b 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.private-memory.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.private-memory.ll
@@ -13,7 +13,7 @@
; GCN-LABEL: {{^}}work_item_info:
; GCN-NOT: v0
-; GCN: v_add_{{[iu]}}32_e32 [[RESULT:v[0-9]+]], vcc, v0, v{{[0-9]+}}
+; GCN: v_add_{{[iu]}}32_e32 [[RESULT:v[0-9]+]], vcc, v{{[0-9]+}}, v0
; GCN: buffer_store_dword [[RESULT]]
define amdgpu_kernel void @work_item_info(i32 addrspace(1)* %out, i32 %in) {
entry:
diff --git a/llvm/test/CodeGen/AMDGPU/bfe-patterns.ll b/llvm/test/CodeGen/AMDGPU/bfe-patterns.ll
index 69237cf..4d47bda 100644
--- a/llvm/test/CodeGen/AMDGPU/bfe-patterns.ll
+++ b/llvm/test/CodeGen/AMDGPU/bfe-patterns.ll
@@ -24,11 +24,8 @@
; GCN: {{buffer|flat}}_load_dword [[WIDTH:v[0-9]+]]
; GCN: v_sub_{{[iu]}}32_e32 [[SUB:v[0-9]+]], vcc, 32, [[WIDTH]]
-; SI-NEXT: v_lshl_b32_e32 [[SHL:v[0-9]+]], [[SRC]], [[SUB]]
-; SI-NEXT: v_lshr_b32_e32 [[BFE:v[0-9]+]], [[SHL]], [[SUB]]
-
-; VI-NEXT: v_lshlrev_b32_e32 [[SHL:v[0-9]+]], [[SUB]], [[SRC]]
-; VI-NEXT: v_lshrrev_b32_e32 [[BFE:v[0-9]+]], [[SUB]], [[SHL]]
+; GCN-NEXT: v_lshlrev_b32_e32 [[SHL:v[0-9]+]], [[SUB]], [[SRC]]
+; GCN-NEXT: v_lshrrev_b32_e32 [[BFE:v[0-9]+]], [[SUB]], [[SHL]]
; GCN: [[BFE]]
; GCN: [[SHL]]
@@ -100,11 +97,8 @@
; GCN: {{buffer|flat}}_load_dword [[WIDTH:v[0-9]+]]
; GCN: v_sub_{{[iu]}}32_e32 [[SUB:v[0-9]+]], vcc, 32, [[WIDTH]]
-; SI-NEXT: v_lshl_b32_e32 [[SHL:v[0-9]+]], [[SRC]], [[SUB]]
-; SI-NEXT: v_ashr_i32_e32 [[BFE:v[0-9]+]], [[SHL]], [[SUB]]
-
-; VI-NEXT: v_lshlrev_b32_e32 [[SHL:v[0-9]+]], [[SUB]], [[SRC]]
-; VI-NEXT: v_ashrrev_i32_e32 [[BFE:v[0-9]+]], [[SUB]], [[SHL]]
+; GCN-NEXT: v_lshlrev_b32_e32 [[SHL:v[0-9]+]], [[SUB]], [[SRC]]
+; GCN-NEXT: v_ashrrev_i32_e32 [[BFE:v[0-9]+]], [[SUB]], [[SHL]]
; GCN: [[BFE]]
; GCN: [[SHL]]
diff --git a/llvm/test/CodeGen/AMDGPU/ctpop64.ll b/llvm/test/CodeGen/AMDGPU/ctpop64.ll
index 00011cd..1b053c6 100644
--- a/llvm/test/CodeGen/AMDGPU/ctpop64.ll
+++ b/llvm/test/CodeGen/AMDGPU/ctpop64.ll
@@ -188,7 +188,7 @@
; GCN-DAG: v_bcnt_u32_b32{{(_e64)*}} [[MIDRESULT2:v[0-9]+]], v[[VAL0]], 0
; GCN-DAG: v_bcnt_u32_b32{{(_e32)*(_e64)*}} [[MIDRESULT3:v[0-9]+]], v{{[0-9]+}}, [[MIDRESULT2]]
-; GCN: v_add_{{[iu]}}32_e32 [[RESULT:v[0-9]+]], vcc, [[MIDRESULT1]], [[MIDRESULT2]]
+; GCN: v_add_{{[iu]}}32_e32 [[RESULT:v[0-9]+]], vcc, [[MIDRESULT2]], [[MIDRESULT1]]
; GCN: buffer_store_dword [[RESULT]],
; GCN: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/extract-lowbits.ll b/llvm/test/CodeGen/AMDGPU/extract-lowbits.ll
index b8c5ae0..243ec53 100644
--- a/llvm/test/CodeGen/AMDGPU/extract-lowbits.ll
+++ b/llvm/test/CodeGen/AMDGPU/extract-lowbits.ll
@@ -169,8 +169,8 @@
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_sub_i32_e32 v1, vcc, 32, v1
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_lshl_b32_e32 v0, v0, v1
-; SI-NEXT: v_lshr_b32_e32 v0, v0, v1
+; SI-NEXT: v_lshlrev_b32_e32 v0, v1, v0
+; SI-NEXT: v_lshrrev_b32_e32 v0, v1, v0
; SI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bzhi32_d1_indexzext:
diff --git a/llvm/test/CodeGen/AMDGPU/fabs.f16.ll b/llvm/test/CodeGen/AMDGPU/fabs.f16.ll
index 6b8eb91..d1d3169 100644
--- a/llvm/test/CodeGen/AMDGPU/fabs.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fabs.f16.ll
@@ -102,11 +102,10 @@
; GCN-LABEL: {{^}}v_fabs_fold_self_v2f16:
; GCN: {{flat|global}}_load_dword [[VAL:v[0-9]+]]
-; CI: v_lshrrev_b32_e32 v{{[0-9]+}}, 16, v{{[0-9]+}}
-; CI: v_lshrrev_b32_e32 v{{[0-9]+}}, 16, v{{[0-9]+}}
-; CI: v_cvt_f32_f16_e32
-; CI: v_cvt_f32_f16_e32
-; CI: v_mul_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
+; CI: v_lshrrev_b32_e32 [[VREG:v[0-9]+]], 16, v{{[0-9]+}}
+; CI: v_cvt_f32_f16_e32 [[NORM:v[0-9]+]], [[VREG]]
+; CI: v_cvt_f32_f16_e64 [[ABS:v[0-9]+]], {{\|}}[[VREG]]{{\|}}
+; CI: v_mul_f32_e32 v{{[0-9]+}}, [[ABS]], [[NORM]]
; CI: v_cvt_f16_f32
; CI: v_mul_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
; CI: v_cvt_f16_f32
diff --git a/llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll b/llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll
index 9d732e9..d9b2533 100644
--- a/llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll
+++ b/llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll
@@ -286,7 +286,7 @@
; CI: v_and_b32_e32 [[AND:v[0-9]+]], 0xffff, [[VEC]]
; CI: v_or_b32_e32 [[RES:v[0-9]+]], 0x3e70000, [[AND]]
-; VI: v_or_b32_sdwa [[RES:v[0-9]+]], [[VEC]], [[K]] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI: v_or_b32_sdwa [[RES:v[0-9]+]], [[K]], [[VEC]] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GCN: {{flat|global}}_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RES]]
define amdgpu_kernel void @v_insertelement_v2i16_1(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) #0 {
@@ -306,7 +306,7 @@
; CI: v_and_b32_e32 [[ELT0:v[0-9]+]], 0xffff, [[VEC]]
; GFX9: v_and_b32_e32 [[ELT0:v[0-9]+]], 0xffff, [[VEC]]
; CI: v_or_b32_e32 [[RES:v[0-9]+]], 0xfff10000, [[ELT0]]
-; VI: v_or_b32_sdwa [[RES:v[0-9]+]], [[VEC]], [[K]] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI: v_or_b32_sdwa [[RES:v[0-9]+]], [[K]], [[VEC]] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9: v_lshl_or_b32 [[RES:v[0-9]+]], -15, 16, [[ELT0]]
; GCN: {{flat|global}}_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RES]]
define amdgpu_kernel void @v_insertelement_v2i16_1_inlineimm(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) #0 {
@@ -373,7 +373,7 @@
; CI: v_and_b32_e32 [[AND:v[0-9]+]], 0xffff, [[VEC]]
; CI: v_or_b32_e32 [[RES:v[0-9]+]], 0x45000000, [[AND]]
-; VI: v_or_b32_sdwa [[RES:v[0-9]+]], [[VEC]], [[K]] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI: v_or_b32_sdwa [[RES:v[0-9]+]], [[K]], [[VEC]] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GCN: {{flat|global}}_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RES]]
define amdgpu_kernel void @v_insertelement_v2f16_1(<2 x half> addrspace(1)* %out, <2 x half> addrspace(1)* %in) #0 {
@@ -393,7 +393,7 @@
; CI: v_and_b32_e32 [[ELT0:v[0-9]+]], 0xffff, [[VEC]]
; GFX9: v_and_b32_e32 [[ELT0:v[0-9]+]], 0xffff, [[VEC]]
; CI: v_or_b32_e32 [[RES:v[0-9]+]], 0x230000, [[ELT0]]
-; VI: v_or_b32_sdwa [[RES:v[0-9]+]], [[VEC]], [[K]] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI: v_or_b32_sdwa [[RES:v[0-9]+]], [[K]], [[VEC]] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9: v_lshl_or_b32 [[RES:v[0-9]+]], 35, 16, [[ELT0]]
; GCN: {{flat|global}}_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RES]]
define amdgpu_kernel void @v_insertelement_v2f16_1_inlineimm(<2 x half> addrspace(1)* %out, <2 x half> addrspace(1)* %in) #0 {
@@ -534,7 +534,7 @@
; VI: s_lshl_b32 [[VAL_HI:s[0-9]+]], [[VAL]], 16
; VI-DAG: v_mov_b32_e32 [[COPY_VAL:v[0-9]+]], [[VAL_HI]]
-; VI: v_or_b32_sdwa v[[INS_HALF:[0-9]+]], v[[LO]], [[COPY_VAL]] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI: v_or_b32_sdwa v[[INS_HALF:[0-9]+]], [[COPY_VAL]], v[[LO]] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; CI: s_lshl_b32 [[VAL_HI:s[0-9]+]], [[VAL]], 16
; CI: v_and_b32_e32 [[AND:v[0-9]+]], 0xffff, v[[LO]]
@@ -588,7 +588,7 @@
; VI: s_lshl_b32 [[VAL_HI:s[0-9]+]], [[VAL]], 16
; VI-DAG: v_mov_b32_e32 [[COPY_VAL:v[0-9]+]], [[VAL_HI]]
-; VI: v_or_b32_sdwa v[[INS_HI:[0-9]+]], v[[HI]], [[COPY_VAL]] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI: v_or_b32_sdwa v[[INS_HI:[0-9]+]], [[COPY_VAL]], v[[HI]] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; CI: s_lshl_b32 [[VAL_HI:s[0-9]+]], [[VAL]], 16
; CI: v_and_b32_e32 [[AND:v[0-9]+]], 0xffff, v[[HI]]
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.update.dpp.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.update.dpp.ll
index d328b10..244fa67 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.update.dpp.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.update.dpp.ll
@@ -15,9 +15,8 @@
}
; VI-LABEL: {{^}}dpp_test1:
-; VI-OPT: v_add_u32_e32 [[REG:v[0-9]+]], vcc, v{{[0-9]+}}, v{{[0-9]+}}
+; VI: v_add_u32_e32 [[REG:v[0-9]+]], vcc, v{{[0-9]+}}, v{{[0-9]+}}
; VI-NOOPT: v_mov_b32_e32 v{{[0-9]+}}, 0
-; VI-NOOPT: v_mov_b32_e32 [[REG:v[0-9]+]], v{{[0-9]+}}
; VI-NEXT: s_nop 0
; VI-NEXT: s_nop 0
; VI-NEXT: v_mov_b32_dpp v2, [[REG]] quad_perm:[1,0,3,2] row_mask:0xf bank_mask:0xf
diff --git a/llvm/test/CodeGen/AMDGPU/shift-i128.ll b/llvm/test/CodeGen/AMDGPU/shift-i128.ll
index d9ba442..cd7b2fe 100644
--- a/llvm/test/CodeGen/AMDGPU/shift-i128.ll
+++ b/llvm/test/CodeGen/AMDGPU/shift-i128.ll
@@ -5,24 +5,22 @@
; GCN-LABEL: v_shl_i128_vv:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_lshl_b64 v[5:6], v[0:1], v4
-; GCN-NEXT: v_lshl_b64 v[7:8], v[2:3], v4
+; GCN-NEXT: v_lshl_b64 v[5:6], v[2:3], v4
; GCN-NEXT: v_sub_i32_e32 v9, vcc, 64, v4
; GCN-NEXT: v_subrev_i32_e32 v11, vcc, 64, v4
-; GCN-NEXT: v_cmp_gt_u32_e32 vcc, 64, v4
-; GCN-NEXT: v_cndmask_b32_e32 v6, 0, v6, vcc
-; GCN-NEXT: v_cndmask_b32_e32 v5, 0, v5, vcc
+; GCN-NEXT: v_lshl_b64 v[7:8], v[0:1], v4
; GCN-NEXT: v_lshr_b64 v[9:10], v[0:1], v9
; GCN-NEXT: v_lshl_b64 v[0:1], v[0:1], v11
-; GCN-NEXT: v_or_b32_e32 v7, v7, v9
-; GCN-NEXT: v_or_b32_e32 v8, v8, v10
-; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v8, vcc
-; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v7, vcc
-; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v4
-; GCN-NEXT: v_cndmask_b32_e32 v3, v1, v3, vcc
-; GCN-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc
-; GCN-NEXT: v_mov_b32_e32 v0, v5
-; GCN-NEXT: v_mov_b32_e32 v1, v6
+; GCN-NEXT: v_or_b32_e32 v6, v6, v10
+; GCN-NEXT: v_or_b32_e32 v5, v5, v9
+; GCN-NEXT: v_cmp_gt_u32_e32 vcc, 64, v4
+; GCN-NEXT: v_cndmask_b32_e32 v6, v1, v6, vcc
+; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc
+; GCN-NEXT: v_cndmask_b32_e32 v1, 0, v8, vcc
+; GCN-NEXT: v_cmp_eq_u32_e64 s[6:7], 0, v4
+; GCN-NEXT: v_cndmask_b32_e64 v3, v6, v3, s[6:7]
+; GCN-NEXT: v_cndmask_b32_e64 v2, v0, v2, s[6:7]
+; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v7, vcc
; GCN-NEXT: s_setpc_b64 s[30:31]
%shl = shl i128 %lhs, %rhs
ret i128 %shl
@@ -32,25 +30,24 @@
; GCN-LABEL: v_lshr_i128_vv:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_lshr_b64 v[5:6], v[2:3], v4
-; GCN-NEXT: v_lshr_b64 v[7:8], v[0:1], v4
+; GCN-NEXT: v_lshr_b64 v[5:6], v[0:1], v4
; GCN-NEXT: v_sub_i32_e32 v9, vcc, 64, v4
; GCN-NEXT: v_subrev_i32_e32 v11, vcc, 64, v4
-; GCN-NEXT: v_cmp_gt_u32_e32 vcc, 64, v4
-; GCN-NEXT: v_cndmask_b32_e32 v6, 0, v6, vcc
-; GCN-NEXT: v_cndmask_b32_e32 v5, 0, v5, vcc
+; GCN-NEXT: v_lshr_b64 v[7:8], v[2:3], v4
; GCN-NEXT: v_lshl_b64 v[9:10], v[2:3], v9
; GCN-NEXT: v_lshr_b64 v[2:3], v[2:3], v11
-; GCN-NEXT: v_or_b32_e32 v7, v7, v9
-; GCN-NEXT: v_or_b32_e32 v8, v8, v10
-; GCN-NEXT: v_cndmask_b32_e32 v3, v3, v8, vcc
-; GCN-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc
-; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v4
-; GCN-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
-; GCN-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
-; GCN-NEXT: v_mov_b32_e32 v2, v5
-; GCN-NEXT: v_mov_b32_e32 v3, v6
+; GCN-NEXT: v_or_b32_e32 v6, v6, v10
+; GCN-NEXT: v_or_b32_e32 v5, v5, v9
+; GCN-NEXT: v_cmp_gt_u32_e32 vcc, 64, v4
+; GCN-NEXT: v_cndmask_b32_e32 v6, v3, v6, vcc
+; GCN-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc
+; GCN-NEXT: v_cndmask_b32_e32 v3, 0, v8, vcc
+; GCN-NEXT: v_cmp_eq_u32_e64 s[6:7], 0, v4
+; GCN-NEXT: v_cndmask_b32_e64 v1, v6, v1, s[6:7]
+; GCN-NEXT: v_cndmask_b32_e64 v0, v2, v0, s[6:7]
+; GCN-NEXT: v_cndmask_b32_e32 v2, 0, v7, vcc
; GCN-NEXT: s_setpc_b64 s[30:31]
+
%shl = lshr i128 %lhs, %rhs
ret i128 %shl
}
@@ -69,8 +66,8 @@
; GCN-NEXT: v_cndmask_b32_e32 v5, v9, v5, vcc
; GCN-NEXT: v_lshl_b64 v[9:10], v[2:3], v10
; GCN-NEXT: v_ashr_i64 v[2:3], v[2:3], v11
-; GCN-NEXT: v_or_b32_e32 v7, v7, v9
; GCN-NEXT: v_or_b32_e32 v8, v8, v10
+; GCN-NEXT: v_or_b32_e32 v7, v7, v9
; GCN-NEXT: v_cndmask_b32_e32 v3, v3, v8, vcc
; GCN-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v4
@@ -497,19 +494,19 @@
; GCN-NEXT: v_lshl_b64 v[16:17], v[2:3], v8
; GCN-NEXT: v_sub_i32_e32 v18, vcc, 64, v8
; GCN-NEXT: v_lshr_b64 v[18:19], v[0:1], v18
-; GCN-NEXT: v_or_b32_e32 v20, v16, v18
-; GCN-NEXT: v_or_b32_e32 v21, v17, v19
+; GCN-NEXT: v_or_b32_e32 v20, v17, v19
+; GCN-NEXT: v_or_b32_e32 v21, v16, v18
; GCN-NEXT: v_sub_i32_e32 v16, vcc, 64, v12
; GCN-NEXT: v_lshr_b64 v[16:17], v[4:5], v16
; GCN-NEXT: v_lshl_b64 v[18:19], v[6:7], v12
-; GCN-NEXT: v_or_b32_e32 v16, v18, v16
; GCN-NEXT: v_or_b32_e32 v17, v19, v17
+; GCN-NEXT: v_or_b32_e32 v16, v18, v16
; GCN-NEXT: v_cmp_eq_u64_e64 s[6:7], 0, v[10:11]
-; GCN-NEXT: v_or_b32_e32 v10, v8, v10
; GCN-NEXT: v_or_b32_e32 v11, v9, v11
+; GCN-NEXT: v_or_b32_e32 v10, v8, v10
; GCN-NEXT: v_cmp_eq_u64_e64 s[8:9], 0, v[14:15]
-; GCN-NEXT: v_or_b32_e32 v14, v12, v14
; GCN-NEXT: v_or_b32_e32 v15, v13, v15
+; GCN-NEXT: v_or_b32_e32 v14, v12, v14
; GCN-NEXT: v_cmp_gt_u64_e64 s[10:11], 64, v[8:9]
; GCN-NEXT: v_subrev_i32_e32 v18, vcc, 64, v8
; GCN-NEXT: v_lshl_b64 v[8:9], v[0:1], v8
@@ -519,8 +516,8 @@
; GCN-NEXT: v_lshl_b64 v[12:13], v[4:5], v12
; GCN-NEXT: v_lshl_b64 v[4:5], v[4:5], v18
; GCN-NEXT: s_and_b64 vcc, s[6:7], s[10:11]
-; GCN-NEXT: v_cndmask_b32_e32 v18, v1, v21, vcc
-; GCN-NEXT: v_cndmask_b32_e32 v19, v0, v20, vcc
+; GCN-NEXT: v_cndmask_b32_e32 v18, v1, v20, vcc
+; GCN-NEXT: v_cndmask_b32_e32 v19, v0, v21, vcc
; GCN-NEXT: s_and_b64 s[6:7], s[8:9], s[12:13]
; GCN-NEXT: v_cndmask_b32_e64 v17, v5, v17, s[6:7]
; GCN-NEXT: v_cndmask_b32_e64 v4, v4, v16, s[6:7]
@@ -546,19 +543,19 @@
; GCN-NEXT: v_lshr_b64 v[16:17], v[0:1], v8
; GCN-NEXT: v_sub_i32_e32 v18, vcc, 64, v8
; GCN-NEXT: v_lshl_b64 v[18:19], v[2:3], v18
-; GCN-NEXT: v_or_b32_e32 v20, v16, v18
-; GCN-NEXT: v_or_b32_e32 v21, v17, v19
+; GCN-NEXT: v_or_b32_e32 v20, v17, v19
+; GCN-NEXT: v_or_b32_e32 v21, v16, v18
; GCN-NEXT: v_sub_i32_e32 v16, vcc, 64, v12
; GCN-NEXT: v_lshl_b64 v[16:17], v[6:7], v16
; GCN-NEXT: v_lshr_b64 v[18:19], v[4:5], v12
-; GCN-NEXT: v_or_b32_e32 v16, v18, v16
; GCN-NEXT: v_or_b32_e32 v17, v19, v17
+; GCN-NEXT: v_or_b32_e32 v16, v18, v16
; GCN-NEXT: v_cmp_eq_u64_e64 s[6:7], 0, v[10:11]
-; GCN-NEXT: v_or_b32_e32 v10, v8, v10
; GCN-NEXT: v_or_b32_e32 v11, v9, v11
+; GCN-NEXT: v_or_b32_e32 v10, v8, v10
; GCN-NEXT: v_cmp_eq_u64_e64 s[8:9], 0, v[14:15]
-; GCN-NEXT: v_or_b32_e32 v14, v12, v14
; GCN-NEXT: v_or_b32_e32 v15, v13, v15
+; GCN-NEXT: v_or_b32_e32 v14, v12, v14
; GCN-NEXT: v_cmp_gt_u64_e64 s[10:11], 64, v[8:9]
; GCN-NEXT: v_subrev_i32_e32 v18, vcc, 64, v8
; GCN-NEXT: v_lshr_b64 v[8:9], v[2:3], v8
@@ -568,8 +565,8 @@
; GCN-NEXT: v_lshr_b64 v[12:13], v[6:7], v12
; GCN-NEXT: v_lshr_b64 v[6:7], v[6:7], v18
; GCN-NEXT: s_and_b64 vcc, s[6:7], s[10:11]
-; GCN-NEXT: v_cndmask_b32_e32 v18, v3, v21, vcc
-; GCN-NEXT: v_cndmask_b32_e32 v19, v2, v20, vcc
+; GCN-NEXT: v_cndmask_b32_e32 v18, v3, v20, vcc
+; GCN-NEXT: v_cndmask_b32_e32 v19, v2, v21, vcc
; GCN-NEXT: s_and_b64 s[6:7], s[8:9], s[12:13]
; GCN-NEXT: v_cndmask_b32_e64 v17, v7, v17, s[6:7]
; GCN-NEXT: v_cndmask_b32_e64 v6, v6, v16, s[6:7]
@@ -595,25 +592,25 @@
; GCN-NEXT: v_lshr_b64 v[16:17], v[0:1], v8
; GCN-NEXT: v_sub_i32_e32 v18, vcc, 64, v8
; GCN-NEXT: v_lshl_b64 v[18:19], v[2:3], v18
-; GCN-NEXT: v_or_b32_e32 v20, v16, v18
-; GCN-NEXT: v_or_b32_e32 v21, v17, v19
+; GCN-NEXT: v_or_b32_e32 v20, v17, v19
+; GCN-NEXT: v_or_b32_e32 v21, v16, v18
; GCN-NEXT: v_sub_i32_e32 v16, vcc, 64, v12
; GCN-NEXT: v_lshl_b64 v[16:17], v[6:7], v16
; GCN-NEXT: v_lshr_b64 v[18:19], v[4:5], v12
-; GCN-NEXT: v_or_b32_e32 v18, v18, v16
; GCN-NEXT: v_or_b32_e32 v19, v19, v17
+; GCN-NEXT: v_or_b32_e32 v18, v18, v16
; GCN-NEXT: v_cmp_eq_u64_e64 s[6:7], 0, v[10:11]
-; GCN-NEXT: v_or_b32_e32 v10, v8, v10
; GCN-NEXT: v_or_b32_e32 v11, v9, v11
+; GCN-NEXT: v_or_b32_e32 v10, v8, v10
; GCN-NEXT: v_cmp_eq_u64_e64 s[8:9], 0, v[14:15]
-; GCN-NEXT: v_or_b32_e32 v14, v12, v14
; GCN-NEXT: v_or_b32_e32 v15, v13, v15
+; GCN-NEXT: v_or_b32_e32 v14, v12, v14
; GCN-NEXT: v_cmp_gt_u64_e64 s[10:11], 64, v[8:9]
; GCN-NEXT: v_subrev_i32_e32 v9, vcc, 64, v8
; GCN-NEXT: v_ashr_i64 v[16:17], v[2:3], v9
; GCN-NEXT: s_and_b64 s[6:7], s[6:7], s[10:11]
-; GCN-NEXT: v_cndmask_b32_e64 v17, v17, v21, s[6:7]
-; GCN-NEXT: v_cndmask_b32_e64 v16, v16, v20, s[6:7]
+; GCN-NEXT: v_cndmask_b32_e64 v17, v17, v20, s[6:7]
+; GCN-NEXT: v_cndmask_b32_e64 v16, v16, v21, s[6:7]
; GCN-NEXT: v_cmp_gt_u64_e64 s[10:11], 64, v[12:13]
; GCN-NEXT: v_ashr_i64 v[8:9], v[2:3], v8
; GCN-NEXT: v_ashrrev_i32_e32 v20, 31, v3
diff --git a/llvm/test/CodeGen/AMDGPU/shl.v2i16.ll b/llvm/test/CodeGen/AMDGPU/shl.v2i16.ll
index ce6125d..b116e2e 100644
--- a/llvm/test/CodeGen/AMDGPU/shl.v2i16.ll
+++ b/llvm/test/CodeGen/AMDGPU/shl.v2i16.ll
@@ -50,7 +50,7 @@
; CI: v_lshrrev_b32_e32 v{{[0-9]+}}, 16, [[LHS]]
; CI: v_lshrrev_b32_e32 v{{[0-9]+}}, 16, v{{[0-9]+}}
; CI: v_lshlrev_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
-; CI: v_lshl_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
+; CI: v_lshlrev_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
; CI: v_lshlrev_b32_e32 v{{[0-9]+}}, 16, v{{[0-9]+}}
; CI: v_and_b32_e32 v{{[0-9]+}}, [[MASK]], v{{[0-9]+}}
; CI: v_or_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
diff --git a/llvm/test/CodeGen/AMDGPU/sibling-call.ll b/llvm/test/CodeGen/AMDGPU/sibling-call.ll
index fb1f5ef..efc0108 100644
--- a/llvm/test/CodeGen/AMDGPU/sibling-call.ll
+++ b/llvm/test/CodeGen/AMDGPU/sibling-call.ll
@@ -6,7 +6,7 @@
; FIXME: Why is this commuted only sometimes?
; GCN-LABEL: {{^}}i32_fastcc_i32_i32:
; GCN: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CIVI-NEXT: v_add_{{i|u}}32_e32 v0, vcc, v1, v0
+; CIVI-NEXT: v_add_{{i|u}}32_e32 v0, vcc, v0, v1
; GFX9-NEXT: v_add_u32_e32 v0, v0, v1
; GCN-NEXT: s_setpc_b64
define fastcc i32 @i32_fastcc_i32_i32(i32 %arg0, i32 %arg1) #1 {
@@ -16,7 +16,7 @@
; GCN-LABEL: {{^}}i32_fastcc_i32_i32_stack_object:
; GCN: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CIVI-NEXT: v_add_{{i|u}}32_e32 v0, vcc, v1, v0
+; CIVI-NEXT: v_add_{{i|u}}32_e32 v0, vcc, v0, v1
; GFX9-NEXT: v_add_u32_e32 v0, v0, v1
; GCN: s_mov_b32 s5, s32
; GCN: buffer_store_dword v{{[0-9]+}}, off, s[0:3], s5 offset:24
@@ -88,7 +88,7 @@
; GCN-NEXT: buffer_load_dword v1, off, s[0:3], s5 offset:4
; GCN-NEXT: s_waitcnt vmcnt(0)
-; CIVI-NEXT: v_add_{{i|u}}32_e32 v0, vcc, v1, v0
+; CIVI-NEXT: v_add_{{i|u}}32_e32 v0, vcc, v0, v1
; GFX9-NEXT: v_add_u32_e32 v0, v0, v1
; GCN-NEXT: s_setpc_b64 s[30:31]
@@ -130,9 +130,9 @@
; GCN-DAG: buffer_load_dword [[LOAD_0:v[0-9]+]], off, s[0:3], s5 offset:4
; GCN-DAG: buffer_load_dword [[LOAD_1:v[0-9]+]], off, s[0:3], s5 offset:8
-; CIVI-NEXT: v_add_{{i|u}}32_e32 v0, vcc, v1, v0
-; CIVI: v_add_{{i|u}}32_e32 v0, vcc, [[LOAD_0]], v0
-; CIVI: v_add_{{i|u}}32_e32 v0, vcc, [[LOAD_1]], v0
+; CIVI-NEXT: v_add_{{i|u}}32_e32 v0, vcc, v0, v1
+; CIVI: v_add_{{i|u}}32_e32 v0, vcc, v0, [[LOAD_0]]
+; CIVI: v_add_{{i|u}}32_e32 v0, vcc, v0, [[LOAD_1]]
; GFX9-NEXT: v_add_u32_e32 v0, v0, v1
diff --git a/llvm/test/CodeGen/AMDGPU/sub.ll b/llvm/test/CodeGen/AMDGPU/sub.ll
index fb1cbe7..4bd346d 100644
--- a/llvm/test/CodeGen/AMDGPU/sub.ll
+++ b/llvm/test/CodeGen/AMDGPU/sub.ll
@@ -93,7 +93,7 @@
}
; FUNC-LABEL: {{^}}test_sub_i16:
-; SI: v_subrev_i32_e32 v{{[0-9]+}}, vcc,
+; SI: v_sub_i32_e32 v{{[0-9]+}}, vcc,
; GFX89: v_sub_u16_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
define amdgpu_kernel void @test_sub_i16(i16 addrspace(1)* %out, i16 addrspace(1)* %in) {
%tid = call i32 @llvm.r600.read.tidig.x()