Revert "[mips] Promote the result of SETCC nodes to GPR width."
This reverts commit r262316.
It seems that my change breaks an out-of-tree chromium buildbot, so
I'm reverting this in order to investigate the situation further.
llvm-svn: 262387
diff --git a/llvm/test/CodeGen/Mips/octeon.ll b/llvm/test/CodeGen/Mips/octeon.ll
index 2b413d7..499ce3c 100644
--- a/llvm/test/CodeGen/Mips/octeon.ll
+++ b/llvm/test/CodeGen/Mips/octeon.ll
@@ -32,8 +32,10 @@
; OCTEON: jr $ra
; OCTEON: seq $2, $4, $5
; MIPS64: xor $[[T0:[0-9]+]], $4, $5
+; MIPS64: sltiu $[[T1:[0-9]+]], $[[T0]], 1
+; MIPS64: dsll $[[T2:[0-9]+]], $[[T1]], 32
; MIPS64: jr $ra
-; MIPS64: sltiu $2, $[[T0]], 1
+; MIPS64: dsrl $2, $[[T2]], 32
%res = icmp eq i64 %a, %b
%res2 = zext i1 %res to i64
ret i64 %res2
@@ -46,8 +48,10 @@
; OCTEON: seqi $2, $4, 42
; MIPS64: daddiu $[[T0:[0-9]+]], $zero, 42
; MIPS64: xor $[[T1:[0-9]+]], $4, $[[T0]]
+; MIPS64: sltiu $[[T2:[0-9]+]], $[[T1]], 1
+; MIPS64: dsll $[[T3:[0-9]+]], $[[T2]], 32
; MIPS64: jr $ra
-; MIPS64: sltiu $2, $[[T1]], 1
+; MIPS64: dsrl $2, $[[T3]], 32
%res = icmp eq i64 %a, 42
%res2 = zext i1 %res to i64
ret i64 %res2
@@ -59,8 +63,10 @@
; OCTEON: jr $ra
; OCTEON: sne $2, $4, $5
; MIPS64: xor $[[T0:[0-9]+]], $4, $5
+; MIPS64: sltu $[[T1:[0-9]+]], $zero, $[[T0]]
+; MIPS64: dsll $[[T2:[0-9]+]], $[[T1]], 32
; MIPS64: jr $ra
-; MIPS64: sltu $2, $zero, $[[T0]]
+; MIPS64: dsrl $2, $[[T2]], 32
%res = icmp ne i64 %a, %b
%res2 = zext i1 %res to i64
ret i64 %res2
@@ -73,8 +79,10 @@
; OCTEON: snei $2, $4, 42
; MIPS64: daddiu $[[T0:[0-9]+]], $zero, 42
; MIPS64: xor $[[T1:[0-9]+]], $4, $[[T0]]
+; MIPS64: sltu $[[T2:[0-9]+]], $zero, $[[T1]]
+; MIPS64: dsll $[[T3:[0-9]+]], $[[T2]], 32
; MIPS64: jr $ra
-; MIPS64: sltu $2, $zero, $[[T1]]
+; MIPS64: dsrl $2, $[[T3]], 32
%res = icmp ne i64 %a, 42
%res2 = zext i1 %res to i64
ret i64 %res2