AMDGPU: Fix assert on n inline asm constraint
llvm-svn: 310515
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
index 36028f7..ec1e53a 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
@@ -1017,20 +1017,29 @@
bool AMDGPUAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
unsigned AsmVariant,
const char *ExtraCode, raw_ostream &O) {
+ // First try the generic code, which knows about modifiers like 'c' and 'n'.
+ if (!AsmPrinter::PrintAsmOperand(MI, OpNo, AsmVariant, ExtraCode, O))
+ return false;
+
if (ExtraCode && ExtraCode[0]) {
if (ExtraCode[1] != 0)
return true; // Unknown modifier.
switch (ExtraCode[0]) {
- default:
- // See if this is a generic print operand
- return AsmPrinter::PrintAsmOperand(MI, OpNo, AsmVariant, ExtraCode, O);
case 'r':
break;
+ default:
+ return true;
}
}
- AMDGPUInstPrinter::printRegOperand(MI->getOperand(OpNo).getReg(), O,
- *TM.getSubtargetImpl(*MF->getFunction())->getRegisterInfo());
- return false;
+ // TODO: Should be able to support other operand types like globals.
+ const MachineOperand &MO = MI->getOperand(OpNo);
+ if (MO.isReg()) {
+ AMDGPUInstPrinter::printRegOperand(MO.getReg(), O,
+ *MF->getSubtarget().getRegisterInfo());
+ return false;
+ }
+
+ return true;
}
diff --git a/llvm/test/CodeGen/AMDGPU/inline-asm.ll b/llvm/test/CodeGen/AMDGPU/inline-asm.ll
index 75826d5..2856212 100644
--- a/llvm/test/CodeGen/AMDGPU/inline-asm.ll
+++ b/llvm/test/CodeGen/AMDGPU/inline-asm.ll
@@ -246,3 +246,19 @@
store i32 %add, i32 addrspace(1)* undef
ret void
}
+
+; CHECK-LABEL: {{^}}asm_constraint_c_n:
+; CHECK: s_trap 10{{$}}
+define amdgpu_kernel void @asm_constraint_c_n() {
+entry:
+ tail call void asm sideeffect "s_trap ${0:c}", "n"(i32 10) #1
+ ret void
+}
+
+; CHECK-LABEL: {{^}}asm_constraint_n_n:
+; CHECK: s_trap -10{{$}}
+define amdgpu_kernel void @asm_constraint_n_n() {
+entry:
+ tail call void asm sideeffect "s_trap ${0:n}", "n"(i32 10) #1
+ ret void
+}