commit 36cdcfadcf57ff8f253b0053137f198187fe85c6
author Matt Arsenault <Matthew.Arsenault@amd.com> Thu Aug 02 13:43:42 2018 +0000
committer Matt Arsenault <Matthew.Arsenault@amd.com> Thu Aug 02 13:43:42 2018 +0000
tree 8a07173bbab6fa97688d1bde6943f506d6d7bfb9
parent 467505bd315640a4f1885605ea3965d3d6f81bad

AMDGPU: Fix scalarizing v4f16 fcanonicalize

llvm-svn: 338714

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index e970f0b..0df268d 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -589,6 +589,7 @@
     setOperationAction(ISD::FMUL, MVT::v4f16, Custom);
     setOperationAction(ISD::FMINNUM, MVT::v4f16, Custom);
     setOperationAction(ISD::FMAXNUM, MVT::v4f16, Custom);
+    setOperationAction(ISD::FCANONICALIZE, MVT::v4f16, Custom);
 
     setOperationAction(ISD::SELECT, MVT::v4i16, Custom);
     setOperationAction(ISD::SELECT, MVT::v4f16, Custom);
@@ -3575,6 +3576,7 @@
     return lowerDEBUGTRAP(Op, DAG);
   case ISD::FABS:
   case ISD::FNEG:
+  case ISD::FCANONICALIZE:
     return splitUnaryVectorOp(Op, DAG);
   case ISD::SHL:
   case ISD::SRA: