[MIPS][MSA] Convert vector integer min/max opcodes to use generic implementation
Found while investigating D43338
Simon^3 - the LLVM project needs more Simons.
Differential Revision: https://reviews.llvm.org/D43433
llvm-svn: 325447
diff --git a/llvm/lib/Target/Mips/MipsSEISelLowering.cpp b/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
index f7d7e2a..deb65bc 100644
--- a/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
+++ b/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
@@ -331,8 +331,12 @@
setOperationAction(ISD::SRA, Ty, Legal);
setOperationAction(ISD::SRL, Ty, Legal);
setOperationAction(ISD::SUB, Ty, Legal);
+ setOperationAction(ISD::SMAX, Ty, Legal);
+ setOperationAction(ISD::SMIN, Ty, Legal);
setOperationAction(ISD::UDIV, Ty, Legal);
setOperationAction(ISD::UREM, Ty, Legal);
+ setOperationAction(ISD::UMAX, Ty, Legal);
+ setOperationAction(ISD::UMIN, Ty, Legal);
setOperationAction(ISD::VECTOR_SHUFFLE, Ty, Custom);
setOperationAction(ISD::VSELECT, Ty, Legal);
setOperationAction(ISD::XOR, Ty, Legal);
@@ -890,46 +894,7 @@
static SDValue performVSELECTCombine(SDNode *N, SelectionDAG &DAG) {
EVT Ty = N->getValueType(0);
- if (Ty.is128BitVector() && Ty.isInteger()) {
- // Try the following combines:
- // (vselect (setcc $a, $b, SETLT), $b, $a)) -> (vsmax $a, $b)
- // (vselect (setcc $a, $b, SETLE), $b, $a)) -> (vsmax $a, $b)
- // (vselect (setcc $a, $b, SETLT), $a, $b)) -> (vsmin $a, $b)
- // (vselect (setcc $a, $b, SETLE), $a, $b)) -> (vsmin $a, $b)
- // (vselect (setcc $a, $b, SETULT), $b, $a)) -> (vumax $a, $b)
- // (vselect (setcc $a, $b, SETULE), $b, $a)) -> (vumax $a, $b)
- // (vselect (setcc $a, $b, SETULT), $a, $b)) -> (vumin $a, $b)
- // (vselect (setcc $a, $b, SETULE), $a, $b)) -> (vumin $a, $b)
- // SETGT/SETGE/SETUGT/SETUGE variants of these will show up initially but
- // will be expanded to equivalent SETLT/SETLE/SETULT/SETULE versions by the
- // legalizer.
- SDValue Op0 = N->getOperand(0);
-
- if (Op0->getOpcode() != ISD::SETCC)
- return SDValue();
-
- ISD::CondCode CondCode = cast<CondCodeSDNode>(Op0->getOperand(2))->get();
- bool Signed;
-
- if (CondCode == ISD::SETLT || CondCode == ISD::SETLE)
- Signed = true;
- else if (CondCode == ISD::SETULT || CondCode == ISD::SETULE)
- Signed = false;
- else
- return SDValue();
-
- SDValue Op1 = N->getOperand(1);
- SDValue Op2 = N->getOperand(2);
- SDValue Op0Op0 = Op0->getOperand(0);
- SDValue Op0Op1 = Op0->getOperand(1);
-
- if (Op1 == Op0Op0 && Op2 == Op0Op1)
- return DAG.getNode(Signed ? MipsISD::VSMIN : MipsISD::VUMIN, SDLoc(N),
- Ty, Op1, Op2);
- else if (Op1 == Op0Op1 && Op2 == Op0Op0)
- return DAG.getNode(Signed ? MipsISD::VSMAX : MipsISD::VUMAX, SDLoc(N),
- Ty, Op1, Op2);
- } else if ((Ty == MVT::v2i16) || (Ty == MVT::v4i8)) {
+ if (Ty == MVT::v2i16 || Ty == MVT::v4i8) {
SDValue SetCC = N->getOperand(0);
if (SetCC.getOpcode() != MipsISD::SETCC_DSP)
@@ -1919,49 +1884,49 @@
case Intrinsic::mips_max_s_h:
case Intrinsic::mips_max_s_w:
case Intrinsic::mips_max_s_d:
- return DAG.getNode(MipsISD::VSMAX, DL, Op->getValueType(0),
+ return DAG.getNode(ISD::SMAX, DL, Op->getValueType(0),
Op->getOperand(1), Op->getOperand(2));
case Intrinsic::mips_max_u_b:
case Intrinsic::mips_max_u_h:
case Intrinsic::mips_max_u_w:
case Intrinsic::mips_max_u_d:
- return DAG.getNode(MipsISD::VUMAX, DL, Op->getValueType(0),
+ return DAG.getNode(ISD::UMAX, DL, Op->getValueType(0),
Op->getOperand(1), Op->getOperand(2));
case Intrinsic::mips_maxi_s_b:
case Intrinsic::mips_maxi_s_h:
case Intrinsic::mips_maxi_s_w:
case Intrinsic::mips_maxi_s_d:
- return DAG.getNode(MipsISD::VSMAX, DL, Op->getValueType(0),
+ return DAG.getNode(ISD::SMAX, DL, Op->getValueType(0),
Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG, true));
case Intrinsic::mips_maxi_u_b:
case Intrinsic::mips_maxi_u_h:
case Intrinsic::mips_maxi_u_w:
case Intrinsic::mips_maxi_u_d:
- return DAG.getNode(MipsISD::VUMAX, DL, Op->getValueType(0),
+ return DAG.getNode(ISD::UMAX, DL, Op->getValueType(0),
Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
case Intrinsic::mips_min_s_b:
case Intrinsic::mips_min_s_h:
case Intrinsic::mips_min_s_w:
case Intrinsic::mips_min_s_d:
- return DAG.getNode(MipsISD::VSMIN, DL, Op->getValueType(0),
+ return DAG.getNode(ISD::SMIN, DL, Op->getValueType(0),
Op->getOperand(1), Op->getOperand(2));
case Intrinsic::mips_min_u_b:
case Intrinsic::mips_min_u_h:
case Intrinsic::mips_min_u_w:
case Intrinsic::mips_min_u_d:
- return DAG.getNode(MipsISD::VUMIN, DL, Op->getValueType(0),
+ return DAG.getNode(ISD::UMIN, DL, Op->getValueType(0),
Op->getOperand(1), Op->getOperand(2));
case Intrinsic::mips_mini_s_b:
case Intrinsic::mips_mini_s_h:
case Intrinsic::mips_mini_s_w:
case Intrinsic::mips_mini_s_d:
- return DAG.getNode(MipsISD::VSMIN, DL, Op->getValueType(0),
+ return DAG.getNode(ISD::SMIN, DL, Op->getValueType(0),
Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG, true));
case Intrinsic::mips_mini_u_b:
case Intrinsic::mips_mini_u_h:
case Intrinsic::mips_mini_u_w:
case Intrinsic::mips_mini_u_d:
- return DAG.getNode(MipsISD::VUMIN, DL, Op->getValueType(0),
+ return DAG.getNode(ISD::UMIN, DL, Op->getValueType(0),
Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
case Intrinsic::mips_mod_s_b:
case Intrinsic::mips_mod_s_h: