commit 38bbf81ade2fa94018db2f0777fa19de71c78f41
author Dorit Nuzman <dorit.nuzman@intel.com> Sun Oct 14 08:50:06 2018 +0000
committer Dorit Nuzman <dorit.nuzman@intel.com> Sun Oct 14 08:50:06 2018 +0000
tree 6e26fb98d4d69d913a700cd79ea468b9d0f59194
parent 74587a0e489dec97780404f064b7768c7ab6df22

recommit 344472 after fixing build failure on ARM and PPC.

llvm-svn: 344475

llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp

diff --git a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
index b0da9b5..f67bacc 100644
--- a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
@@ -473,7 +473,12 @@
                                            unsigned Factor,
                                            ArrayRef<unsigned> Indices,
                                            unsigned Alignment,
-                                           unsigned AddressSpace) {
+                                           unsigned AddressSpace,
+                                           bool IsMasked) {
+  if (IsMasked)
+    return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices,
+                                             Alignment, AddressSpace, IsMasked);
+
   assert(isa<VectorType>(VecTy) &&
          "Expect a vector type for interleaved memory op");