commit 39bf39f35c208109f6d5907708ee53dee2878bed
author Derek Schuff <dschuff@google.com> Tue Aug 02 23:16:09 2016 +0000
committer Derek Schuff <dschuff@google.com> Tue Aug 02 23:16:09 2016 +0000
tree 92c88047132b9387bfac686662ba7d8a3b9e0abc
parent 02a1e973a80adce224cd950bb2b5b2c78622829a

[WebAssembly] Initial SIMD128 support.

Kicks off the implementation of wasm SIMD128 support (spec:
https://github.com/stoklund/portable-simd/blob/master/portable-simd.md),
adding support for add, sub, mul for i8x16, i16x8, i32x4, and f32x4.

The spec is WIP, and might change in the near future.

Patch by João Porto

Differential Revision: https://reviews.llvm.org/D22686

llvm-svn: 277543

llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp

diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp
index 0aa3b62..5ff0085 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp
@@ -418,6 +418,8 @@
     return WebAssembly::TEE_LOCAL_F32;
   if (RC == &WebAssembly::F64RegClass)
     return WebAssembly::TEE_LOCAL_F64;
+  if (RC == &WebAssembly::V128RegClass)
+    return WebAssembly::TEE_LOCAL_V128;
   llvm_unreachable("Unexpected register class");
 }
 
@@ -765,7 +767,11 @@
         if (Def->getOpcode() == WebAssembly::ARGUMENT_I32 ||
             Def->getOpcode() == WebAssembly::ARGUMENT_I64 ||
             Def->getOpcode() == WebAssembly::ARGUMENT_F32 ||
-            Def->getOpcode() == WebAssembly::ARGUMENT_F64)
+            Def->getOpcode() == WebAssembly::ARGUMENT_F64 ||
+            Def->getOpcode() == WebAssembly::ARGUMENT_v16i8 ||
+            Def->getOpcode() == WebAssembly::ARGUMENT_v8i16 ||
+            Def->getOpcode() == WebAssembly::ARGUMENT_v4i32 ||
+            Def->getOpcode() == WebAssembly::ARGUMENT_v4f32)
           continue;
 
         // Decide which strategy to take. Prefer to move a single-use value