[mips][microMIPS] Extending size reduction pass with LWP and SWP
Author: milena.vujosevic.janicic
Reviewers: sdardis
The patch extends size reduction pass for MicroMIPS.
It introduces reduction of two instructions into one instruction:
Two SW instructions are transformed into one SWP instrucition.
Two LW instructions are transformed into one LWP instrucition.
Differential Revision: https://reviews.llvm.org/D39115
llvm-svn: 334595
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/or.ll b/llvm/test/CodeGen/Mips/llvm-ir/or.ll
index 7f9998e..ce22f08 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/or.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/or.ll
@@ -176,8 +176,7 @@
;
; MM32-LABEL: or_i128:
; MM32: # %bb.0: # %entry
-; MM32-NEXT: lw $3, 20($sp)
-; MM32-NEXT: lw $2, 16($sp)
+; MM32-NEXT: lwp $2, 16($sp)
; MM32-NEXT: or16 $2, $4
; MM32-NEXT: or16 $3, $5
; MM32-NEXT: lw $4, 24($sp)