[Hexagon] Add inline-asm constraint 'a' for modifier register class
For example
asm ("memw(%0++%1) = %2" : : "r"(addr),"a"(mod),"r"(val) : "memory")
llvm-svn: 308761
diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
index 1291af8..f02cd6d 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
@@ -2923,7 +2923,11 @@
case 'q':
case 'v':
if (Subtarget.useHVXOps())
- return C_Register;
+ return C_RegisterClass;
+ break;
+ case 'a':
+ return C_RegisterClass;
+ default:
break;
}
}
@@ -2951,6 +2955,9 @@
case MVT::f64:
return std::make_pair(0U, &Hexagon::DoubleRegsRegClass);
}
+ break;
+ case 'a': // M0-M1
+ return std::make_pair(0U, &Hexagon::ModRegsRegClass);
case 'q': // q0-q3
switch (VT.getSizeInBits()) {
default:
@@ -2960,6 +2967,7 @@
case 1024:
return std::make_pair(0U, &Hexagon::VecPredRegs128BRegClass);
}
+ break;
case 'v': // V0-V31
switch (VT.getSizeInBits()) {
default:
@@ -2973,7 +2981,7 @@
case 2048:
return std::make_pair(0U, &Hexagon::VecDblRegs128BRegClass);
}
-
+ break;
default:
llvm_unreachable("Unknown asm register class");
}